Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T12
1	0	Covered	T2,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Covered	T2,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T16,T26

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T16,T26
1	0	Covered	T14,T16,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T14,T16,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T12
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	677427420	551225047	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	677427420	3064761	0	0
GntImpliesValid_A	677427420	3064761	0	0
GrantKnown_A	677427420	551225047	0	0
IdxKnown_A	677427420	551225047	0	0
IndexIsCorrect_A	677427420	3064761	0	0
LockArbDecision_A	677427420	0	0	0
NoReadyValidNoGrant_A	677427420	0	0	0
ReadyAndValidImplyGrant_A	677427420	3064761	0	0
ReqAndReadyImplyGrant_A	677427420	3064761	0	0
ReqImpliesValid_A	677427420	3064761	0	0
ReqStaysHighUntilGranted0_M	677427420	0	0	0
RoundRobin_A	677427420	3	0	926
ValidKnown_A	677427420	551225047	0	0
gen_data_port_assertion.DataFlow_A	677427420	3064761	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	551225047	0	0
T1	5533	5100	0	0
T2	11352	11302	0	0
T3	256505	228727	0	0
T4	877036	767681	0	0
T5	6873	6625	0	0
T6	287546	230576	0	0
T7	16137	10674	0	0
T8	126343	111477	0	0
T9	38985	25284	0	0
T10	1639	1561	0	0
T12	261806	124896	0	0
T13	15462	15462	0	0
T14	0	313259	0	0
T15	0	116524	0	0
T16	0	611166	0	0
T23	0	43256	0	0
T26	0	141024	0	0
T27	139106	133208	0	0
T28	0	94256	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	3064761	0	0
T2	11352	143	0	0
T3	228801	832	0	0
T4	767738	832	0	0
T5	6701	832	0	0
T6	230738	832	0	0
T7	10729	832	0	0
T8	112227	1075	0	0
T9	25637	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	130903	7110	0	0
T13	15462	1600	0	0
T14	123220	9658	0	0
T15	116636	0	0	0
T16	613255	2821	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	10306	0	0
T27	0	5116	0	0
T28	98389	0	0	0
T34	0	4374	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T51	0	10871	0	0
T52	0	225	0	0
T53	0	3029	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	3064761	0	0
T2	11352	143	0	0
T3	228801	832	0	0
T4	767738	832	0	0
T5	6701	832	0	0
T6	230738	832	0	0
T7	10729	832	0	0
T8	112227	1075	0	0
T9	25637	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	130903	7110	0	0
T13	15462	1600	0	0
T14	123220	9658	0	0
T15	116636	0	0	0
T16	613255	2821	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	10306	0	0
T27	0	5116	0	0
T28	98389	0	0	0
T34	0	4374	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T51	0	10871	0	0
T52	0	225	0	0
T53	0	3029	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	551225047	0	0
T1	5533	5100	0	0
T2	11352	11302	0	0
T3	256505	228727	0	0
T4	877036	767681	0	0
T5	6873	6625	0	0
T6	287546	230576	0	0
T7	16137	10674	0	0
T8	126343	111477	0	0
T9	38985	25284	0	0
T10	1639	1561	0	0
T12	261806	124896	0	0
T13	15462	15462	0	0
T14	0	313259	0	0
T15	0	116524	0	0
T16	0	611166	0	0
T23	0	43256	0	0
T26	0	141024	0	0
T27	139106	133208	0	0
T28	0	94256	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	551225047	0	0
T1	5533	5100	0	0
T2	11352	11302	0	0
T3	256505	228727	0	0
T4	877036	767681	0	0
T5	6873	6625	0	0
T6	287546	230576	0	0
T7	16137	10674	0	0
T8	126343	111477	0	0
T9	38985	25284	0	0
T10	1639	1561	0	0
T12	261806	124896	0	0
T13	15462	15462	0	0
T14	0	313259	0	0
T15	0	116524	0	0
T16	0	611166	0	0
T23	0	43256	0	0
T26	0	141024	0	0
T27	139106	133208	0	0
T28	0	94256	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	3064761	0	0
T2	11352	143	0	0
T3	228801	832	0	0
T4	767738	832	0	0
T5	6701	832	0	0
T6	230738	832	0	0
T7	10729	832	0	0
T8	112227	1075	0	0
T9	25637	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	130903	7110	0	0
T13	15462	1600	0	0
T14	123220	9658	0	0
T15	116636	0	0	0
T16	613255	2821	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	10306	0	0
T27	0	5116	0	0
T28	98389	0	0	0
T34	0	4374	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T51	0	10871	0	0
T52	0	225	0	0
T53	0	3029	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	3064761	0	0
T2	11352	143	0	0
T3	228801	832	0	0
T4	767738	832	0	0
T5	6701	832	0	0
T6	230738	832	0	0
T7	10729	832	0	0
T8	112227	1075	0	0
T9	25637	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	130903	7110	0	0
T13	15462	1600	0	0
T14	123220	9658	0	0
T15	116636	0	0	0
T16	613255	2821	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	10306	0	0
T27	0	5116	0	0
T28	98389	0	0	0
T34	0	4374	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T51	0	10871	0	0
T52	0	225	0	0
T53	0	3029	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	3064761	0	0
T2	11352	143	0	0
T3	228801	832	0	0
T4	767738	832	0	0
T5	6701	832	0	0
T6	230738	832	0	0
T7	10729	832	0	0
T8	112227	1075	0	0
T9	25637	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	130903	7110	0	0
T13	15462	1600	0	0
T14	123220	9658	0	0
T15	116636	0	0	0
T16	613255	2821	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	10306	0	0
T27	0	5116	0	0
T28	98389	0	0	0
T34	0	4374	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T51	0	10871	0	0
T52	0	225	0	0
T53	0	3029	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	3064761	0	0
T2	11352	143	0	0
T3	228801	832	0	0
T4	767738	832	0	0
T5	6701	832	0	0
T6	230738	832	0	0
T7	10729	832	0	0
T8	112227	1075	0	0
T9	25637	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	130903	7110	0	0
T13	15462	1600	0	0
T14	123220	9658	0	0
T15	116636	0	0	0
T16	613255	2821	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	10306	0	0
T27	0	5116	0	0
T28	98389	0	0	0
T34	0	4374	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T51	0	10871	0	0
T52	0	225	0	0
T53	0	3029	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	3	0	926
T54	424105	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	274797	0	0	1
T58	136731	0	0	1
T59	153970	0	0	1
T60	14605	0	0	1
T61	38686	0	0	1
T62	72644	0	0	1
T63	8974	0	0	1
T64	4566	0	0	1
T65	114907	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	551225047	0	0
T1	5533	5100	0	0
T2	11352	11302	0	0
T3	256505	228727	0	0
T4	877036	767681	0	0
T5	6873	6625	0	0
T6	287546	230576	0	0
T7	16137	10674	0	0
T8	126343	111477	0	0
T9	38985	25284	0	0
T10	1639	1561	0	0
T12	261806	124896	0	0
T13	15462	15462	0	0
T14	0	313259	0	0
T15	0	116524	0	0
T16	0	611166	0	0
T23	0	43256	0	0
T26	0	141024	0	0
T27	139106	133208	0	0
T28	0	94256	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	677427420	3064761	0	0
T2	11352	143	0	0
T3	228801	832	0	0
T4	767738	832	0	0
T5	6701	832	0	0
T6	230738	832	0	0
T7	10729	832	0	0
T8	112227	1075	0	0
T9	25637	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	130903	7110	0	0
T13	15462	1600	0	0
T14	123220	9658	0	0
T15	116636	0	0	0
T16	613255	2821	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	10306	0	0
T27	0	5116	0	0
T28	98389	0	0	0
T34	0	4374	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T51	0	10871	0	0
T52	0	225	0	0
T53	0	3029	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T12
1	0	Covered	T2,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Covered	T2,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	124908630	24411014	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	124908630	606657	0	0
GntImpliesValid_A	124908630	606657	0	0
GrantKnown_A	124908630	24411014	0	0
IdxKnown_A	124908630	24411014	0	0
IndexIsCorrect_A	124908630	606657	0	0
LockArbDecision_A	124908630	0	0	0
NoReadyValidNoGrant_A	124908630	0	0	0
ReadyAndValidImplyGrant_A	124908630	606657	0	0
ReqAndReadyImplyGrant_A	124908630	606657	0	0
ReqImpliesValid_A	124908630	606657	0	0
ReqStaysHighUntilGranted0_M	124908630	0	0	0
RoundRobin_A	124908630	0	0	0
ValidKnown_A	124908630	24411014	0	0
gen_data_port_assertion.DataFlow_A	124908630	606657	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	24411014	0	0
T1	1366	1008	0	0
T2	1704	1704	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	13432	0	0
T9	13348	0	0	0
T12	130903	124896	0	0
T14	0	212808	0	0
T16	0	9768	0	0
T23	0	43256	0	0
T26	0	141024	0	0
T27	0	133208	0	0
T28	0	94256	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	606657	0	0
T2	1704	98	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	758	0	0
T9	13348	0	0	0
T12	130903	4652	0	0
T13	15462	0	0	0
T14	0	8203	0	0
T16	0	404	0	0
T26	0	6613	0	0
T27	0	5116	0	0
T34	0	3327	0	0
T51	0	4306	0	0
T52	0	225	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	606657	0	0
T2	1704	98	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	758	0	0
T9	13348	0	0	0
T12	130903	4652	0	0
T13	15462	0	0	0
T14	0	8203	0	0
T16	0	404	0	0
T26	0	6613	0	0
T27	0	5116	0	0
T34	0	3327	0	0
T51	0	4306	0	0
T52	0	225	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	24411014	0	0
T1	1366	1008	0	0
T2	1704	1704	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	13432	0	0
T9	13348	0	0	0
T12	130903	124896	0	0
T14	0	212808	0	0
T16	0	9768	0	0
T23	0	43256	0	0
T26	0	141024	0	0
T27	0	133208	0	0
T28	0	94256	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	24411014	0	0
T1	1366	1008	0	0
T2	1704	1704	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	13432	0	0
T9	13348	0	0	0
T12	130903	124896	0	0
T14	0	212808	0	0
T16	0	9768	0	0
T23	0	43256	0	0
T26	0	141024	0	0
T27	0	133208	0	0
T28	0	94256	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	606657	0	0
T2	1704	98	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	758	0	0
T9	13348	0	0	0
T12	130903	4652	0	0
T13	15462	0	0	0
T14	0	8203	0	0
T16	0	404	0	0
T26	0	6613	0	0
T27	0	5116	0	0
T34	0	3327	0	0
T51	0	4306	0	0
T52	0	225	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	606657	0	0
T2	1704	98	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	758	0	0
T9	13348	0	0	0
T12	130903	4652	0	0
T13	15462	0	0	0
T14	0	8203	0	0
T16	0	404	0	0
T26	0	6613	0	0
T27	0	5116	0	0
T34	0	3327	0	0
T51	0	4306	0	0
T52	0	225	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	606657	0	0
T2	1704	98	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	758	0	0
T9	13348	0	0	0
T12	130903	4652	0	0
T13	15462	0	0	0
T14	0	8203	0	0
T16	0	404	0	0
T26	0	6613	0	0
T27	0	5116	0	0
T34	0	3327	0	0
T51	0	4306	0	0
T52	0	225	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	606657	0	0
T2	1704	98	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	758	0	0
T9	13348	0	0	0
T12	130903	4652	0	0
T13	15462	0	0	0
T14	0	8203	0	0
T16	0	404	0	0
T26	0	6613	0	0
T27	0	5116	0	0
T34	0	3327	0	0
T51	0	4306	0	0
T52	0	225	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	24411014	0	0
T1	1366	1008	0	0
T2	1704	1704	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	13432	0	0
T9	13348	0	0	0
T12	130903	124896	0	0
T14	0	212808	0	0
T16	0	9768	0	0
T23	0	43256	0	0
T26	0	141024	0	0
T27	0	133208	0	0
T28	0	94256	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	606657	0	0
T2	1704	98	0	0
T3	27704	0	0	0
T4	109298	0	0	0
T5	172	0	0	0
T6	56808	0	0	0
T7	5408	0	0	0
T8	14116	758	0	0
T9	13348	0	0	0
T12	130903	4652	0	0
T13	15462	0	0	0
T14	0	8203	0	0
T16	0	404	0	0
T26	0	6613	0	0
T27	0	5116	0	0
T34	0	3327	0	0
T51	0	4306	0	0
T52	0	225	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T16,T26

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T16,T26
1	0	Covered	T14,T16,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T14,T16,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T14,T16,T26
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	124908630	99288428	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	124908630	534987	0	0
GntImpliesValid_A	124908630	534987	0	0
GrantKnown_A	124908630	99288428	0	0
IdxKnown_A	124908630	99288428	0	0
IndexIsCorrect_A	124908630	534987	0	0
LockArbDecision_A	124908630	0	0	0
NoReadyValidNoGrant_A	124908630	0	0	0
ReadyAndValidImplyGrant_A	124908630	534987	0	0
ReqAndReadyImplyGrant_A	124908630	534987	0	0
ReqImpliesValid_A	124908630	534987	0	0
ReqStaysHighUntilGranted0_M	124908630	0	0	0
RoundRobin_A	124908630	0	0	0
ValidKnown_A	124908630	99288428	0	0
gen_data_port_assertion.DataFlow_A	124908630	534987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	99288428	0	0
T3	27704	27704	0	0
T4	109298	109298	0	0
T5	172	172	0	0
T6	56808	56704	0	0
T7	5408	5408	0	0
T8	14116	0	0	0
T9	13348	13068	0	0
T12	130903	0	0	0
T13	15462	15462	0	0
T14	0	100451	0	0
T15	0	116524	0	0
T16	0	601398	0	0
T27	139106	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	534987	0	0
T14	123220	1455	0	0
T15	116636	0	0	0
T16	613255	2417	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	3693	0	0
T28	98389	0	0	0
T34	0	1047	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T49	86060	0	0	0
T51	0	6565	0	0
T53	0	3029	0	0
T66	0	2043	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	534987	0	0
T14	123220	1455	0	0
T15	116636	0	0	0
T16	613255	2417	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	3693	0	0
T28	98389	0	0	0
T34	0	1047	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T49	86060	0	0	0
T51	0	6565	0	0
T53	0	3029	0	0
T66	0	2043	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	99288428	0	0
T3	27704	27704	0	0
T4	109298	109298	0	0
T5	172	172	0	0
T6	56808	56704	0	0
T7	5408	5408	0	0
T8	14116	0	0	0
T9	13348	13068	0	0
T12	130903	0	0	0
T13	15462	15462	0	0
T14	0	100451	0	0
T15	0	116524	0	0
T16	0	601398	0	0
T27	139106	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	99288428	0	0
T3	27704	27704	0	0
T4	109298	109298	0	0
T5	172	172	0	0
T6	56808	56704	0	0
T7	5408	5408	0	0
T8	14116	0	0	0
T9	13348	13068	0	0
T12	130903	0	0	0
T13	15462	15462	0	0
T14	0	100451	0	0
T15	0	116524	0	0
T16	0	601398	0	0
T27	139106	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	534987	0	0
T14	123220	1455	0	0
T15	116636	0	0	0
T16	613255	2417	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	3693	0	0
T28	98389	0	0	0
T34	0	1047	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T49	86060	0	0	0
T51	0	6565	0	0
T53	0	3029	0	0
T66	0	2043	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	534987	0	0
T14	123220	1455	0	0
T15	116636	0	0	0
T16	613255	2417	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	3693	0	0
T28	98389	0	0	0
T34	0	1047	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T49	86060	0	0	0
T51	0	6565	0	0
T53	0	3029	0	0
T66	0	2043	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	534987	0	0
T14	123220	1455	0	0
T15	116636	0	0	0
T16	613255	2417	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	3693	0	0
T28	98389	0	0	0
T34	0	1047	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T49	86060	0	0	0
T51	0	6565	0	0
T53	0	3029	0	0
T66	0	2043	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	534987	0	0
T14	123220	1455	0	0
T15	116636	0	0	0
T16	613255	2417	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	3693	0	0
T28	98389	0	0	0
T34	0	1047	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T49	86060	0	0	0
T51	0	6565	0	0
T53	0	3029	0	0
T66	0	2043	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	99288428	0	0
T3	27704	27704	0	0
T4	109298	109298	0	0
T5	172	172	0	0
T6	56808	56704	0	0
T7	5408	5408	0	0
T8	14116	0	0	0
T9	13348	13068	0	0
T12	130903	0	0	0
T13	15462	15462	0	0
T14	0	100451	0	0
T15	0	116524	0	0
T16	0	601398	0	0
T27	139106	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124908630	534987	0	0
T14	123220	1455	0	0
T15	116636	0	0	0
T16	613255	2417	0	0
T23	45888	0	0	0
T24	6300	0	0	0
T25	12408	0	0	0
T26	431153	3693	0	0
T28	98389	0	0	0
T34	0	1047	0	0
T39	0	2687	0	0
T40	0	6186	0	0
T41	0	5667	0	0
T48	21532	0	0	0
T49	86060	0	0	0
T51	0	6565	0	0
T53	0	3029	0	0
T66	0	2043	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T8,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T12
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427610160	427525605	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	427610160	1923117	0	0
GntImpliesValid_A	427610160	1923117	0	0
GrantKnown_A	427610160	427525605	0	0
IdxKnown_A	427610160	427525605	0	0
IndexIsCorrect_A	427610160	1923117	0	0
LockArbDecision_A	427610160	0	0	0
NoReadyValidNoGrant_A	427610160	0	0	0
ReadyAndValidImplyGrant_A	427610160	1923117	0	0
ReqAndReadyImplyGrant_A	427610160	1923117	0	0
ReqImpliesValid_A	427610160	1923117	0	0
ReqStaysHighUntilGranted0_M	427610160	0	0	0
RoundRobin_A	427610160	3	0	926
ValidKnown_A	427610160	427525605	0	0
gen_data_port_assertion.DataFlow_A	427610160	1923117	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	427525605	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	1923117	0	0
T2	9648	45	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	832	0	0
T6	173930	832	0	0
T7	5321	832	0	0
T8	98111	317	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	2458	0	0
T13	0	1600	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	1923117	0	0
T2	9648	45	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	832	0	0
T6	173930	832	0	0
T7	5321	832	0	0
T8	98111	317	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	2458	0	0
T13	0	1600	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	427525605	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	427525605	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	1923117	0	0
T2	9648	45	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	832	0	0
T6	173930	832	0	0
T7	5321	832	0	0
T8	98111	317	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	2458	0	0
T13	0	1600	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	1923117	0	0
T2	9648	45	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	832	0	0
T6	173930	832	0	0
T7	5321	832	0	0
T8	98111	317	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	2458	0	0
T13	0	1600	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	1923117	0	0
T2	9648	45	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	832	0	0
T6	173930	832	0	0
T7	5321	832	0	0
T8	98111	317	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	2458	0	0
T13	0	1600	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	1923117	0	0
T2	9648	45	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	832	0	0
T6	173930	832	0	0
T7	5321	832	0	0
T8	98111	317	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	2458	0	0
T13	0	1600	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	3	0	926
T54	424105	1	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	274797	0	0	1
T58	136731	0	0	1
T59	153970	0	0	1
T60	14605	0	0	1
T61	38686	0	0	1
T62	72644	0	0	1
T63	8974	0	0	1
T64	4566	0	0	1
T65	114907	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	427525605	0	0
T1	4167	4092	0	0
T2	9648	9598	0	0
T3	201097	201023	0	0
T4	658440	658383	0	0
T5	6529	6453	0	0
T6	173930	173872	0	0
T7	5321	5266	0	0
T8	98111	98045	0	0
T9	12289	12216	0	0
T10	1639	1561	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427610160	1923117	0	0
T2	9648	45	0	0
T3	201097	832	0	0
T4	658440	832	0	0
T5	6529	832	0	0
T6	173930	832	0	0
T7	5321	832	0	0
T8	98111	317	0	0
T9	12289	832	0	0
T10	1639	0	0	0
T11	1306	0	0	0
T12	0	2458	0	0
T13	0	1600	0	0