Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
3667 |
0 |
0 |
T91 |
13783 |
201 |
0 |
0 |
T92 |
27829 |
1 |
0 |
0 |
T93 |
7823 |
3 |
0 |
0 |
T94 |
12265 |
134 |
0 |
0 |
T95 |
67796 |
4 |
0 |
0 |
T96 |
19869 |
4 |
0 |
0 |
T97 |
8044 |
95 |
0 |
0 |
T101 |
5878 |
319 |
0 |
0 |
T102 |
1874 |
28 |
0 |
0 |
T110 |
2635 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2192 |
0 |
0 |
T81 |
2199 |
7 |
0 |
0 |
T95 |
67796 |
85 |
0 |
0 |
T116 |
179606 |
408 |
0 |
0 |
T117 |
104649 |
421 |
0 |
0 |
T124 |
9068 |
4 |
0 |
0 |
T146 |
270469 |
683 |
0 |
0 |
T147 |
7547 |
27 |
0 |
0 |
T148 |
9571 |
8 |
0 |
0 |
T149 |
9135 |
18 |
0 |
0 |
T150 |
63112 |
61 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2152 |
0 |
0 |
T82 |
3534 |
8 |
0 |
0 |
T95 |
67796 |
82 |
0 |
0 |
T116 |
179606 |
472 |
0 |
0 |
T117 |
104649 |
434 |
0 |
0 |
T124 |
9068 |
2 |
0 |
0 |
T146 |
270469 |
655 |
0 |
0 |
T147 |
7547 |
16 |
0 |
0 |
T148 |
9571 |
7 |
0 |
0 |
T149 |
9135 |
9 |
0 |
0 |
T150 |
63112 |
84 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2511 |
0 |
0 |
T82 |
3534 |
11 |
0 |
0 |
T95 |
67796 |
148 |
0 |
0 |
T116 |
179606 |
409 |
0 |
0 |
T117 |
104649 |
395 |
0 |
0 |
T124 |
9068 |
23 |
0 |
0 |
T146 |
270469 |
654 |
0 |
0 |
T147 |
7547 |
25 |
0 |
0 |
T148 |
9571 |
7 |
0 |
0 |
T149 |
9135 |
9 |
0 |
0 |
T150 |
63112 |
118 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
9131 |
0 |
0 |
T81 |
2199 |
2 |
0 |
0 |
T95 |
67796 |
1642 |
0 |
0 |
T116 |
179606 |
454 |
0 |
0 |
T117 |
104649 |
440 |
0 |
0 |
T124 |
9068 |
70 |
0 |
0 |
T146 |
270469 |
702 |
0 |
0 |
T147 |
7547 |
23 |
0 |
0 |
T148 |
9571 |
8 |
0 |
0 |
T149 |
9135 |
124 |
0 |
0 |
T150 |
63112 |
1185 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
7406 |
0 |
0 |
T81 |
2199 |
2 |
0 |
0 |
T95 |
67796 |
1143 |
0 |
0 |
T116 |
179606 |
440 |
0 |
0 |
T117 |
104649 |
377 |
0 |
0 |
T124 |
9068 |
79 |
0 |
0 |
T146 |
270469 |
626 |
0 |
0 |
T147 |
7547 |
17 |
0 |
0 |
T148 |
9571 |
60 |
0 |
0 |
T149 |
9135 |
7 |
0 |
0 |
T150 |
63112 |
745 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
8331 |
0 |
0 |
T81 |
2199 |
2 |
0 |
0 |
T95 |
67796 |
1667 |
0 |
0 |
T116 |
179606 |
440 |
0 |
0 |
T117 |
104649 |
419 |
0 |
0 |
T124 |
9068 |
61 |
0 |
0 |
T146 |
270469 |
698 |
0 |
0 |
T147 |
7547 |
14 |
0 |
0 |
T148 |
9571 |
7 |
0 |
0 |
T149 |
9135 |
131 |
0 |
0 |
T150 |
63112 |
662 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
8920 |
0 |
0 |
T82 |
3534 |
6 |
0 |
0 |
T95 |
67796 |
1212 |
0 |
0 |
T116 |
179606 |
451 |
0 |
0 |
T117 |
104649 |
450 |
0 |
0 |
T124 |
9068 |
195 |
0 |
0 |
T146 |
270469 |
703 |
0 |
0 |
T147 |
7547 |
31 |
0 |
0 |
T148 |
9571 |
68 |
0 |
0 |
T149 |
9135 |
19 |
0 |
0 |
T150 |
63112 |
1387 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
7460 |
0 |
0 |
T81 |
2199 |
4 |
0 |
0 |
T95 |
67796 |
1073 |
0 |
0 |
T116 |
179606 |
482 |
0 |
0 |
T117 |
104649 |
425 |
0 |
0 |
T124 |
9068 |
62 |
0 |
0 |
T146 |
270469 |
675 |
0 |
0 |
T147 |
7547 |
52 |
0 |
0 |
T148 |
9571 |
84 |
0 |
0 |
T149 |
9135 |
139 |
0 |
0 |
T150 |
63112 |
895 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
8443 |
0 |
0 |
T82 |
3534 |
11 |
0 |
0 |
T95 |
67796 |
919 |
0 |
0 |
T116 |
179606 |
443 |
0 |
0 |
T117 |
104649 |
424 |
0 |
0 |
T124 |
9068 |
169 |
0 |
0 |
T146 |
270469 |
696 |
0 |
0 |
T147 |
7547 |
43 |
0 |
0 |
T148 |
9571 |
90 |
0 |
0 |
T149 |
9135 |
246 |
0 |
0 |
T150 |
63112 |
1010 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
8262 |
0 |
0 |
T82 |
3534 |
6 |
0 |
0 |
T95 |
67796 |
1239 |
0 |
0 |
T116 |
179606 |
465 |
0 |
0 |
T117 |
104649 |
424 |
0 |
0 |
T124 |
9068 |
75 |
0 |
0 |
T146 |
270469 |
723 |
0 |
0 |
T147 |
7547 |
45 |
0 |
0 |
T148 |
9571 |
89 |
0 |
0 |
T149 |
9135 |
23 |
0 |
0 |
T150 |
63112 |
1081 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
7614 |
0 |
0 |
T81 |
2199 |
9 |
0 |
0 |
T95 |
67796 |
1217 |
0 |
0 |
T116 |
179606 |
516 |
0 |
0 |
T117 |
104649 |
423 |
0 |
0 |
T124 |
9068 |
130 |
0 |
0 |
T146 |
270469 |
659 |
0 |
0 |
T147 |
7547 |
18 |
0 |
0 |
T148 |
9571 |
75 |
0 |
0 |
T149 |
9135 |
17 |
0 |
0 |
T150 |
63112 |
828 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
5262 |
0 |
0 |
T81 |
2199 |
8 |
0 |
0 |
T95 |
67796 |
644 |
0 |
0 |
T116 |
179606 |
555 |
0 |
0 |
T117 |
104649 |
464 |
0 |
0 |
T124 |
9068 |
80 |
0 |
0 |
T146 |
270469 |
717 |
0 |
0 |
T147 |
7547 |
30 |
0 |
0 |
T148 |
9571 |
14 |
0 |
0 |
T149 |
9135 |
55 |
0 |
0 |
T150 |
63112 |
699 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4456 |
0 |
0 |
T82 |
3534 |
4 |
0 |
0 |
T95 |
67796 |
485 |
0 |
0 |
T116 |
179606 |
442 |
0 |
0 |
T117 |
104649 |
421 |
0 |
0 |
T124 |
9068 |
32 |
0 |
0 |
T146 |
270469 |
653 |
0 |
0 |
T147 |
7547 |
51 |
0 |
0 |
T148 |
9571 |
3 |
0 |
0 |
T149 |
9135 |
75 |
0 |
0 |
T150 |
63112 |
479 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4455 |
0 |
0 |
T82 |
3534 |
14 |
0 |
0 |
T95 |
67796 |
368 |
0 |
0 |
T116 |
179606 |
474 |
0 |
0 |
T117 |
104649 |
417 |
0 |
0 |
T124 |
9068 |
39 |
0 |
0 |
T146 |
270469 |
656 |
0 |
0 |
T147 |
7547 |
20 |
0 |
0 |
T148 |
9571 |
54 |
0 |
0 |
T149 |
9135 |
65 |
0 |
0 |
T150 |
63112 |
588 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4622 |
0 |
0 |
T81 |
2199 |
7 |
0 |
0 |
T95 |
67796 |
624 |
0 |
0 |
T116 |
179606 |
438 |
0 |
0 |
T117 |
104649 |
364 |
0 |
0 |
T124 |
9068 |
60 |
0 |
0 |
T146 |
270469 |
730 |
0 |
0 |
T147 |
7547 |
21 |
0 |
0 |
T148 |
9571 |
26 |
0 |
0 |
T149 |
9135 |
19 |
0 |
0 |
T150 |
63112 |
463 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4555 |
0 |
0 |
T82 |
3534 |
3 |
0 |
0 |
T95 |
67796 |
530 |
0 |
0 |
T116 |
179606 |
450 |
0 |
0 |
T117 |
104649 |
407 |
0 |
0 |
T124 |
9068 |
35 |
0 |
0 |
T146 |
270469 |
675 |
0 |
0 |
T147 |
7547 |
6 |
0 |
0 |
T148 |
9571 |
61 |
0 |
0 |
T149 |
9135 |
66 |
0 |
0 |
T150 |
63112 |
394 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4330 |
0 |
0 |
T82 |
3534 |
6 |
0 |
0 |
T95 |
67796 |
320 |
0 |
0 |
T116 |
179606 |
522 |
0 |
0 |
T117 |
104649 |
353 |
0 |
0 |
T124 |
9068 |
17 |
0 |
0 |
T146 |
270469 |
681 |
0 |
0 |
T147 |
7547 |
16 |
0 |
0 |
T148 |
9571 |
44 |
0 |
0 |
T149 |
9135 |
12 |
0 |
0 |
T150 |
63112 |
558 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4433 |
0 |
0 |
T82 |
3534 |
3 |
0 |
0 |
T95 |
67796 |
556 |
0 |
0 |
T116 |
179606 |
508 |
0 |
0 |
T117 |
104649 |
393 |
0 |
0 |
T124 |
9068 |
27 |
0 |
0 |
T146 |
270469 |
609 |
0 |
0 |
T147 |
7547 |
19 |
0 |
0 |
T148 |
9571 |
44 |
0 |
0 |
T149 |
9135 |
108 |
0 |
0 |
T150 |
63112 |
557 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4720 |
0 |
0 |
T82 |
3534 |
2 |
0 |
0 |
T95 |
67796 |
738 |
0 |
0 |
T116 |
179606 |
436 |
0 |
0 |
T117 |
104649 |
333 |
0 |
0 |
T124 |
9068 |
40 |
0 |
0 |
T146 |
270469 |
636 |
0 |
0 |
T147 |
7547 |
45 |
0 |
0 |
T148 |
9571 |
57 |
0 |
0 |
T149 |
9135 |
48 |
0 |
0 |
T150 |
63112 |
472 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4487 |
0 |
0 |
T82 |
3534 |
11 |
0 |
0 |
T95 |
67796 |
597 |
0 |
0 |
T116 |
179606 |
414 |
0 |
0 |
T117 |
104649 |
385 |
0 |
0 |
T124 |
9068 |
30 |
0 |
0 |
T146 |
270469 |
648 |
0 |
0 |
T147 |
7547 |
25 |
0 |
0 |
T148 |
9571 |
33 |
0 |
0 |
T149 |
9135 |
40 |
0 |
0 |
T150 |
63112 |
683 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4500 |
0 |
0 |
T81 |
2199 |
2 |
0 |
0 |
T95 |
67796 |
658 |
0 |
0 |
T116 |
179606 |
488 |
0 |
0 |
T117 |
104649 |
374 |
0 |
0 |
T124 |
9068 |
26 |
0 |
0 |
T146 |
270469 |
661 |
0 |
0 |
T147 |
7547 |
21 |
0 |
0 |
T148 |
9571 |
1 |
0 |
0 |
T149 |
9135 |
8 |
0 |
0 |
T150 |
63112 |
606 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4921 |
0 |
0 |
T82 |
3534 |
8 |
0 |
0 |
T95 |
67796 |
710 |
0 |
0 |
T116 |
179606 |
438 |
0 |
0 |
T117 |
104649 |
390 |
0 |
0 |
T124 |
9068 |
28 |
0 |
0 |
T146 |
270469 |
671 |
0 |
0 |
T147 |
7547 |
39 |
0 |
0 |
T148 |
9571 |
55 |
0 |
0 |
T149 |
9135 |
65 |
0 |
0 |
T150 |
63112 |
575 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
5191 |
0 |
0 |
T81 |
2199 |
7 |
0 |
0 |
T82 |
3534 |
9 |
0 |
0 |
T95 |
67796 |
603 |
0 |
0 |
T116 |
179606 |
473 |
0 |
0 |
T117 |
104649 |
483 |
0 |
0 |
T124 |
9068 |
40 |
0 |
0 |
T146 |
270469 |
670 |
0 |
0 |
T147 |
7547 |
9 |
0 |
0 |
T149 |
9135 |
65 |
0 |
0 |
T150 |
63112 |
436 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4331 |
0 |
0 |
T82 |
3534 |
14 |
0 |
0 |
T95 |
67796 |
570 |
0 |
0 |
T116 |
179606 |
428 |
0 |
0 |
T117 |
104649 |
343 |
0 |
0 |
T124 |
9068 |
61 |
0 |
0 |
T146 |
270469 |
714 |
0 |
0 |
T147 |
7547 |
6 |
0 |
0 |
T148 |
9571 |
33 |
0 |
0 |
T149 |
9135 |
46 |
0 |
0 |
T150 |
63112 |
474 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4523 |
0 |
0 |
T82 |
3534 |
2 |
0 |
0 |
T95 |
67796 |
438 |
0 |
0 |
T116 |
179606 |
403 |
0 |
0 |
T117 |
104649 |
476 |
0 |
0 |
T124 |
9068 |
77 |
0 |
0 |
T146 |
270469 |
602 |
0 |
0 |
T147 |
7547 |
1 |
0 |
0 |
T148 |
9571 |
44 |
0 |
0 |
T149 |
9135 |
13 |
0 |
0 |
T150 |
63112 |
725 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4499 |
0 |
0 |
T82 |
3534 |
6 |
0 |
0 |
T95 |
67796 |
482 |
0 |
0 |
T116 |
179606 |
446 |
0 |
0 |
T117 |
104649 |
337 |
0 |
0 |
T124 |
9068 |
29 |
0 |
0 |
T146 |
270469 |
645 |
0 |
0 |
T147 |
7547 |
27 |
0 |
0 |
T148 |
9571 |
49 |
0 |
0 |
T149 |
9135 |
21 |
0 |
0 |
T150 |
63112 |
642 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4653 |
0 |
0 |
T95 |
67796 |
574 |
0 |
0 |
T97 |
8044 |
1 |
0 |
0 |
T116 |
179606 |
412 |
0 |
0 |
T117 |
104649 |
438 |
0 |
0 |
T124 |
9068 |
9 |
0 |
0 |
T146 |
270469 |
654 |
0 |
0 |
T147 |
7547 |
23 |
0 |
0 |
T148 |
9571 |
30 |
0 |
0 |
T149 |
9135 |
75 |
0 |
0 |
T150 |
63112 |
616 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4880 |
0 |
0 |
T82 |
3534 |
15 |
0 |
0 |
T95 |
67796 |
574 |
0 |
0 |
T116 |
179606 |
413 |
0 |
0 |
T117 |
104649 |
380 |
0 |
0 |
T124 |
9068 |
77 |
0 |
0 |
T146 |
270469 |
602 |
0 |
0 |
T147 |
7547 |
18 |
0 |
0 |
T148 |
9571 |
49 |
0 |
0 |
T149 |
9135 |
109 |
0 |
0 |
T150 |
63112 |
537 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4672 |
0 |
0 |
T82 |
3534 |
16 |
0 |
0 |
T95 |
67796 |
464 |
0 |
0 |
T116 |
179606 |
491 |
0 |
0 |
T117 |
104649 |
453 |
0 |
0 |
T124 |
9068 |
24 |
0 |
0 |
T146 |
270469 |
665 |
0 |
0 |
T147 |
7547 |
2 |
0 |
0 |
T148 |
9571 |
80 |
0 |
0 |
T149 |
9135 |
50 |
0 |
0 |
T150 |
63112 |
763 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4808 |
0 |
0 |
T82 |
3534 |
2 |
0 |
0 |
T95 |
67796 |
590 |
0 |
0 |
T116 |
179606 |
381 |
0 |
0 |
T117 |
104649 |
420 |
0 |
0 |
T124 |
9068 |
11 |
0 |
0 |
T146 |
270469 |
728 |
0 |
0 |
T147 |
7547 |
32 |
0 |
0 |
T148 |
9571 |
48 |
0 |
0 |
T149 |
9135 |
95 |
0 |
0 |
T150 |
63112 |
637 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4479 |
0 |
0 |
T95 |
67796 |
502 |
0 |
0 |
T97 |
8044 |
6 |
0 |
0 |
T116 |
179606 |
478 |
0 |
0 |
T117 |
104649 |
408 |
0 |
0 |
T124 |
9068 |
38 |
0 |
0 |
T146 |
270469 |
674 |
0 |
0 |
T147 |
7547 |
8 |
0 |
0 |
T148 |
9571 |
46 |
0 |
0 |
T149 |
9135 |
13 |
0 |
0 |
T150 |
63112 |
591 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4476 |
0 |
0 |
T82 |
3534 |
5 |
0 |
0 |
T91 |
13783 |
4 |
0 |
0 |
T95 |
67796 |
529 |
0 |
0 |
T116 |
179606 |
401 |
0 |
0 |
T117 |
104649 |
416 |
0 |
0 |
T124 |
9068 |
27 |
0 |
0 |
T146 |
270469 |
682 |
0 |
0 |
T148 |
9571 |
22 |
0 |
0 |
T149 |
9135 |
112 |
0 |
0 |
T150 |
63112 |
431 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
5033 |
0 |
0 |
T82 |
3534 |
11 |
0 |
0 |
T95 |
67796 |
516 |
0 |
0 |
T116 |
179606 |
442 |
0 |
0 |
T117 |
104649 |
408 |
0 |
0 |
T124 |
9068 |
19 |
0 |
0 |
T146 |
270469 |
716 |
0 |
0 |
T147 |
7547 |
10 |
0 |
0 |
T148 |
9571 |
71 |
0 |
0 |
T149 |
9135 |
78 |
0 |
0 |
T150 |
63112 |
603 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4452 |
0 |
0 |
T82 |
3534 |
6 |
0 |
0 |
T95 |
67796 |
474 |
0 |
0 |
T116 |
179606 |
460 |
0 |
0 |
T117 |
104649 |
448 |
0 |
0 |
T124 |
9068 |
47 |
0 |
0 |
T146 |
270469 |
629 |
0 |
0 |
T148 |
9571 |
50 |
0 |
0 |
T149 |
9135 |
70 |
0 |
0 |
T150 |
63112 |
535 |
0 |
0 |
T151 |
10745 |
29 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4581 |
0 |
0 |
T82 |
3534 |
7 |
0 |
0 |
T95 |
67796 |
532 |
0 |
0 |
T116 |
179606 |
431 |
0 |
0 |
T117 |
104649 |
366 |
0 |
0 |
T124 |
9068 |
42 |
0 |
0 |
T146 |
270469 |
609 |
0 |
0 |
T147 |
7547 |
6 |
0 |
0 |
T148 |
9571 |
33 |
0 |
0 |
T149 |
9135 |
87 |
0 |
0 |
T150 |
63112 |
684 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2224 |
0 |
0 |
T81 |
2199 |
3 |
0 |
0 |
T95 |
67796 |
107 |
0 |
0 |
T116 |
179606 |
393 |
0 |
0 |
T117 |
104649 |
376 |
0 |
0 |
T124 |
9068 |
2 |
0 |
0 |
T146 |
270469 |
605 |
0 |
0 |
T147 |
7547 |
14 |
0 |
0 |
T148 |
9571 |
12 |
0 |
0 |
T149 |
9135 |
12 |
0 |
0 |
T150 |
63112 |
120 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2305 |
0 |
0 |
T82 |
3534 |
4 |
0 |
0 |
T95 |
67796 |
86 |
0 |
0 |
T116 |
179606 |
411 |
0 |
0 |
T117 |
104649 |
392 |
0 |
0 |
T124 |
9068 |
3 |
0 |
0 |
T146 |
270469 |
642 |
0 |
0 |
T147 |
7547 |
6 |
0 |
0 |
T148 |
9571 |
15 |
0 |
0 |
T149 |
9135 |
11 |
0 |
0 |
T150 |
63112 |
134 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2201 |
0 |
0 |
T82 |
3534 |
9 |
0 |
0 |
T95 |
67796 |
83 |
0 |
0 |
T116 |
179606 |
422 |
0 |
0 |
T117 |
104649 |
348 |
0 |
0 |
T146 |
270469 |
666 |
0 |
0 |
T147 |
7547 |
15 |
0 |
0 |
T148 |
9571 |
21 |
0 |
0 |
T149 |
9135 |
16 |
0 |
0 |
T150 |
63112 |
89 |
0 |
0 |
T151 |
10745 |
3 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2406 |
0 |
0 |
T81 |
2199 |
5 |
0 |
0 |
T95 |
67796 |
131 |
0 |
0 |
T116 |
179606 |
484 |
0 |
0 |
T117 |
104649 |
374 |
0 |
0 |
T124 |
9068 |
11 |
0 |
0 |
T146 |
270469 |
629 |
0 |
0 |
T147 |
7547 |
36 |
0 |
0 |
T148 |
9571 |
10 |
0 |
0 |
T149 |
9135 |
21 |
0 |
0 |
T150 |
63112 |
106 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2690 |
0 |
0 |
T82 |
3534 |
12 |
0 |
0 |
T95 |
67796 |
190 |
0 |
0 |
T116 |
179606 |
441 |
0 |
0 |
T117 |
104649 |
417 |
0 |
0 |
T124 |
9068 |
15 |
0 |
0 |
T146 |
270469 |
745 |
0 |
0 |
T147 |
7547 |
5 |
0 |
0 |
T148 |
9571 |
4 |
0 |
0 |
T149 |
9135 |
8 |
0 |
0 |
T150 |
63112 |
180 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
4514 |
0 |
0 |
T20 |
129774 |
39 |
0 |
0 |
T21 |
5800 |
0 |
0 |
0 |
T31 |
0 |
23 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T38 |
1660 |
0 |
0 |
0 |
T44 |
194072 |
0 |
0 |
0 |
T45 |
0 |
40 |
0 |
0 |
T64 |
0 |
11 |
0 |
0 |
T136 |
0 |
29 |
0 |
0 |
T152 |
0 |
54 |
0 |
0 |
T153 |
0 |
30 |
0 |
0 |
T154 |
0 |
81 |
0 |
0 |
T155 |
0 |
5 |
0 |
0 |
T156 |
845 |
0 |
0 |
0 |
T157 |
60358 |
0 |
0 |
0 |
T158 |
51501 |
0 |
0 |
0 |
T159 |
63373 |
0 |
0 |
0 |
T160 |
150207 |
0 |
0 |
0 |
T161 |
109759 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2380 |
0 |
0 |
T81 |
2199 |
3 |
0 |
0 |
T95 |
67796 |
121 |
0 |
0 |
T116 |
179606 |
462 |
0 |
0 |
T117 |
104649 |
439 |
0 |
0 |
T124 |
9068 |
10 |
0 |
0 |
T146 |
270469 |
652 |
0 |
0 |
T147 |
7547 |
24 |
0 |
0 |
T148 |
9571 |
18 |
0 |
0 |
T149 |
9135 |
20 |
0 |
0 |
T150 |
63112 |
105 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2488 |
0 |
0 |
T81 |
2199 |
6 |
0 |
0 |
T95 |
67796 |
124 |
0 |
0 |
T116 |
179606 |
437 |
0 |
0 |
T117 |
104649 |
394 |
0 |
0 |
T124 |
9068 |
7 |
0 |
0 |
T146 |
270469 |
720 |
0 |
0 |
T147 |
7547 |
30 |
0 |
0 |
T148 |
9571 |
18 |
0 |
0 |
T149 |
9135 |
17 |
0 |
0 |
T150 |
63112 |
102 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2370 |
0 |
0 |
T81 |
2199 |
5 |
0 |
0 |
T95 |
67796 |
75 |
0 |
0 |
T116 |
179606 |
449 |
0 |
0 |
T117 |
104649 |
435 |
0 |
0 |
T124 |
9068 |
8 |
0 |
0 |
T146 |
270469 |
645 |
0 |
0 |
T147 |
7547 |
37 |
0 |
0 |
T148 |
9571 |
18 |
0 |
0 |
T149 |
9135 |
21 |
0 |
0 |
T150 |
63112 |
101 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2114 |
0 |
0 |
T81 |
2199 |
4 |
0 |
0 |
T82 |
3534 |
1 |
0 |
0 |
T95 |
67796 |
97 |
0 |
0 |
T116 |
179606 |
382 |
0 |
0 |
T117 |
104649 |
391 |
0 |
0 |
T124 |
9068 |
1 |
0 |
0 |
T146 |
270469 |
669 |
0 |
0 |
T147 |
7547 |
12 |
0 |
0 |
T149 |
9135 |
20 |
0 |
0 |
T150 |
63112 |
70 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2345 |
0 |
0 |
T91 |
13783 |
7 |
0 |
0 |
T95 |
67796 |
92 |
0 |
0 |
T116 |
179606 |
436 |
0 |
0 |
T117 |
104649 |
413 |
0 |
0 |
T124 |
9068 |
2 |
0 |
0 |
T146 |
270469 |
772 |
0 |
0 |
T147 |
7547 |
18 |
0 |
0 |
T148 |
9571 |
13 |
0 |
0 |
T149 |
9135 |
18 |
0 |
0 |
T150 |
63112 |
84 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2176 |
0 |
0 |
T82 |
3534 |
7 |
0 |
0 |
T95 |
67796 |
57 |
0 |
0 |
T116 |
179606 |
444 |
0 |
0 |
T117 |
104649 |
426 |
0 |
0 |
T146 |
270469 |
651 |
0 |
0 |
T147 |
7547 |
32 |
0 |
0 |
T148 |
9571 |
3 |
0 |
0 |
T149 |
9135 |
9 |
0 |
0 |
T150 |
63112 |
94 |
0 |
0 |
T151 |
10745 |
12 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2754 |
0 |
0 |
T81 |
2199 |
4 |
0 |
0 |
T95 |
67796 |
202 |
0 |
0 |
T116 |
179606 |
460 |
0 |
0 |
T117 |
104649 |
304 |
0 |
0 |
T124 |
9068 |
6 |
0 |
0 |
T146 |
270469 |
661 |
0 |
0 |
T147 |
7547 |
32 |
0 |
0 |
T148 |
9571 |
12 |
0 |
0 |
T149 |
9135 |
16 |
0 |
0 |
T150 |
63112 |
150 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2073 |
0 |
0 |
T82 |
3534 |
4 |
0 |
0 |
T95 |
67796 |
69 |
0 |
0 |
T116 |
179606 |
419 |
0 |
0 |
T117 |
104649 |
377 |
0 |
0 |
T124 |
9068 |
3 |
0 |
0 |
T146 |
270469 |
624 |
0 |
0 |
T147 |
7547 |
26 |
0 |
0 |
T148 |
9571 |
8 |
0 |
0 |
T149 |
9135 |
5 |
0 |
0 |
T150 |
63112 |
97 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2732 |
0 |
0 |
T81 |
2199 |
6 |
0 |
0 |
T95 |
67796 |
220 |
0 |
0 |
T116 |
179606 |
407 |
0 |
0 |
T117 |
104649 |
380 |
0 |
0 |
T124 |
9068 |
11 |
0 |
0 |
T146 |
270469 |
658 |
0 |
0 |
T147 |
7547 |
18 |
0 |
0 |
T148 |
9571 |
10 |
0 |
0 |
T149 |
9135 |
7 |
0 |
0 |
T150 |
63112 |
265 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2325 |
0 |
0 |
T81 |
2199 |
6 |
0 |
0 |
T82 |
3534 |
6 |
0 |
0 |
T95 |
67796 |
87 |
0 |
0 |
T116 |
179606 |
418 |
0 |
0 |
T117 |
104649 |
367 |
0 |
0 |
T146 |
270469 |
667 |
0 |
0 |
T147 |
7547 |
27 |
0 |
0 |
T148 |
9571 |
9 |
0 |
0 |
T149 |
9135 |
30 |
0 |
0 |
T150 |
63112 |
105 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2110 |
0 |
0 |
T81 |
2199 |
5 |
0 |
0 |
T95 |
67796 |
65 |
0 |
0 |
T116 |
179606 |
463 |
0 |
0 |
T117 |
104649 |
381 |
0 |
0 |
T124 |
9068 |
10 |
0 |
0 |
T146 |
270469 |
649 |
0 |
0 |
T147 |
7547 |
27 |
0 |
0 |
T148 |
9571 |
13 |
0 |
0 |
T149 |
9135 |
15 |
0 |
0 |
T150 |
63112 |
70 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2185 |
0 |
0 |
T82 |
3534 |
5 |
0 |
0 |
T95 |
67796 |
65 |
0 |
0 |
T116 |
179606 |
489 |
0 |
0 |
T117 |
104649 |
302 |
0 |
0 |
T124 |
9068 |
10 |
0 |
0 |
T146 |
270469 |
649 |
0 |
0 |
T147 |
7547 |
16 |
0 |
0 |
T148 |
9571 |
2 |
0 |
0 |
T149 |
9135 |
25 |
0 |
0 |
T150 |
63112 |
102 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2072 |
0 |
0 |
T81 |
2199 |
2 |
0 |
0 |
T82 |
3534 |
12 |
0 |
0 |
T95 |
67796 |
84 |
0 |
0 |
T116 |
179606 |
388 |
0 |
0 |
T117 |
104649 |
338 |
0 |
0 |
T146 |
270469 |
713 |
0 |
0 |
T147 |
7547 |
5 |
0 |
0 |
T148 |
9571 |
14 |
0 |
0 |
T149 |
9135 |
19 |
0 |
0 |
T150 |
63112 |
54 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2140 |
0 |
0 |
T82 |
3534 |
4 |
0 |
0 |
T95 |
67796 |
89 |
0 |
0 |
T116 |
179606 |
453 |
0 |
0 |
T117 |
104649 |
435 |
0 |
0 |
T124 |
9068 |
7 |
0 |
0 |
T146 |
270469 |
653 |
0 |
0 |
T147 |
7547 |
22 |
0 |
0 |
T148 |
9571 |
3 |
0 |
0 |
T149 |
9135 |
11 |
0 |
0 |
T150 |
63112 |
71 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2242 |
0 |
0 |
T81 |
2199 |
4 |
0 |
0 |
T95 |
67796 |
96 |
0 |
0 |
T116 |
179606 |
463 |
0 |
0 |
T117 |
104649 |
449 |
0 |
0 |
T124 |
9068 |
10 |
0 |
0 |
T146 |
270469 |
675 |
0 |
0 |
T147 |
7547 |
2 |
0 |
0 |
T148 |
9571 |
2 |
0 |
0 |
T149 |
9135 |
5 |
0 |
0 |
T150 |
63112 |
73 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429973989 |
2210 |
0 |
0 |
T81 |
2199 |
2 |
0 |
0 |
T95 |
67796 |
76 |
0 |
0 |
T116 |
179606 |
449 |
0 |
0 |
T117 |
104649 |
430 |
0 |
0 |
T124 |
9068 |
12 |
0 |
0 |
T146 |
270469 |
677 |
0 |
0 |
T147 |
7547 |
7 |
0 |
0 |
T148 |
9571 |
5 |
0 |
0 |
T149 |
9135 |
5 |
0 |
0 |
T150 |
63112 |
66 |
0 |
0 |