Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1221885960	2534	0	0
SrcPulseCheck_M	396105648	2534	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1221885960	2534	0	0
T2	417688	10	0	0
T3	46004	0	0	0
T4	347744	16	0	0
T5	270543	13	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	8	0	0
T9	145909	11	0	0
T10	187620	0	0	0
T11	417869	0	0	0
T12	384816	7	0	0
T13	0	34	0	0
T22	277894	0	0	0
T23	6016	0	0	0
T24	13442	0	0	0
T25	5442	0	0	0
T26	719608	13	0	0
T27	1293922	13	0	0
T34	225168	3	0	0
T35	0	7	0	0
T36	0	5	0	0
T39	335788	0	0	0
T40	942298	11	0	0
T75	0	7	0	0
T130	0	4	0	0
T131	0	7	0	0
T132	0	7	0	0
T133	0	7	0	0
T134	0	7	0	0
T135	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396105648	2534	0	0
T2	102765	10	0	0
T3	11638	0	0	0
T4	424841	16	0	0
T5	100498	13	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	8	0	0
T9	487630	11	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T12	46526	7	0	0
T13	0	34	0	0
T22	395992	0	0	0
T24	4386	0	0	0
T25	1008	0	0	0
T26	1520712	13	0	0
T27	215766	13	0	0
T34	31360	3	0	0
T35	0	7	0	0
T36	0	5	0	0
T39	163396	0	0	0
T40	778150	11	0	0
T75	0	7	0	0
T130	0	4	0	0
T131	0	7	0	0
T132	0	7	0	0
T133	0	7	0	0
T134	0	7	0	0
T135	0	7	0	0
T136	13704	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T34,T35
1	0	Covered	T12,T34,T35
1	1	Covered	T12,T34,T35

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T34,T35
1	0	Covered	T12,T34,T35
1	1	Covered	T12,T34,T35

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	407295320	192	0	0
SrcPulseCheck_M	132035216	192	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	192	0	0
T12	192408	2	0	0
T22	138947	0	0	0
T23	3008	0	0	0
T24	6721	0	0	0
T25	2721	0	0	0
T26	359804	0	0	0
T27	646961	0	0	0
T34	112584	2	0	0
T35	0	2	0	0
T39	167894	0	0	0
T40	471149	0	0	0
T75	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	192	0	0
T12	23263	2	0	0
T22	197996	0	0	0
T24	2193	0	0	0
T25	504	0	0	0
T26	760356	0	0	0
T27	107883	0	0	0
T34	15680	2	0	0
T35	0	2	0	0
T39	81698	0	0	0
T40	389075	0	0	0
T75	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	6852	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T34,T35
1	0	Covered	T12,T34,T35
1	1	Covered	T12,T35,T75

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T34,T35
1	0	Covered	T12,T35,T75
1	1	Covered	T12,T34,T35

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	407295320	328	0	0
SrcPulseCheck_M	132035216	328	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	328	0	0
T12	192408	5	0	0
T22	138947	0	0	0
T23	3008	0	0	0
T24	6721	0	0	0
T25	2721	0	0	0
T26	359804	0	0	0
T27	646961	0	0	0
T34	112584	1	0	0
T35	0	5	0	0
T39	167894	0	0	0
T40	471149	0	0	0
T75	0	5	0	0
T130	0	2	0	0
T131	0	5	0	0
T132	0	5	0	0
T133	0	5	0	0
T134	0	5	0	0
T135	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	328	0	0
T12	23263	5	0	0
T22	197996	0	0	0
T24	2193	0	0	0
T25	504	0	0	0
T26	760356	0	0	0
T27	107883	0	0	0
T34	15680	1	0	0
T35	0	5	0	0
T39	81698	0	0	0
T40	389075	0	0	0
T75	0	5	0	0
T130	0	2	0	0
T131	0	5	0	0
T132	0	5	0	0
T133	0	5	0	0
T134	0	5	0	0
T135	0	5	0	0
T136	6852	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	407295320	2014	0	0
SrcPulseCheck_M	132035216	2014	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2014	0	0
T2	417688	10	0	0
T3	46004	0	0	0
T4	347744	16	0	0
T5	270543	13	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	8	0	0
T9	145909	11	0	0
T10	187620	0	0	0
T11	417869	0	0	0
T13	0	34	0	0
T26	0	13	0	0
T27	0	13	0	0
T36	0	5	0	0
T40	0	11	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	2014	0	0
T2	102765	10	0	0
T3	11638	0	0	0
T4	424841	16	0	0
T5	100498	13	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	8	0	0
T9	487630	11	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T13	0	34	0	0
T26	0	13	0	0
T27	0	13	0	0
T36	0	5	0	0
T40	0	11	0	0