Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.52	95.20	84.31	97.00		90.62	95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.52	95.20	84.31	97.00		90.62	95.45

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.52	95.20	84.31	97.00		90.62	95.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	98.44	94.08	98.62	89.36	97.28	95.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	97.61	100.00	92.13		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_rst_out_scan_mux	64.81	100.00	44.44				50.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	85.98	100.00	71.43			72.50	100.00
u_passthrough	90.54	94.95	89.22		75.00	93.52	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_intercept_pipe_stg1	100.00	100.00				100.00
u_read_intercept_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	89.30	93.62	90.32		87.50	84.15	90.91
u_reg	99.65	99.53	99.35	100.00		99.35	100.00
u_rst_spi_out_sync	100.00	100.00				100.00
u_s2p	89.38	100.00	78.57			78.95	100.00
u_scanmode_sync	100.00						100.00
u_spi_tpm	92.81	99.28	85.25		91.67	95.68	92.16
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	95.45	100.00	81.82			100.00	100.00
u_spid_status	92.61	100.00	88.46			98.63	83.33
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	89.65	100.00	76.47			96.43	85.71
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.47	82.11	59.19			63.33	81.25
u_tlul2sram_ingress	86.64	88.21	73.90			84.44	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_tpm_rst_out_scan_mux	64.81	100.00	44.44				50.00
u_tpm_rst_out_sync	100.00	100.00				100.00
u_upload	90.79	98.60	71.95		100.00	94.12	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		229	218	95.20
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
ALWAYS	539	4	4	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
ALWAYS	569	0	0
ALWAYS	569	2	2	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	583	0	0
ALWAYS	583	12	12	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	649	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
ALWAYS	828	3	3	100.00
ALWAYS	834	8	8	100.00
ALWAYS	872	9	9	100.00
ALWAYS	896	24	24	100.00
CONT_ASSIGN	964	1	1	100.00
CONT_ASSIGN	965	1	1	100.00
ALWAYS	1028	7	7	100.00
ALWAYS	1041	13	13	100.00
ALWAYS	1078	3	3	100.00
CONT_ASSIGN	1217	1	1	100.00
CONT_ASSIGN	1220	1	1	100.00
CONT_ASSIGN	1224	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1226	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1282	1	0	0.00
CONT_ASSIGN	1313	1	0	0.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1400	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1414	1	1	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1420	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
CONT_ASSIGN	1426	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1435	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1482	1	1	100.00
CONT_ASSIGN	1585	1	0	0.00
CONT_ASSIGN	1593	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1595	1	1	100.00
CONT_ASSIGN	1596	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1600	1	1	100.00
CONT_ASSIGN	1607	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1617	1	1	100.00
CONT_ASSIGN	1618	1	1	100.00
CONT_ASSIGN	1619	1	1	100.00
CONT_ASSIGN	1620	1	1	100.00
CONT_ASSIGN	1621	1	1	100.00
CONT_ASSIGN	1622	1	1	100.00
CONT_ASSIGN	1624	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1631	1	1	100.00
CONT_ASSIGN	1638	1	1	100.00
CONT_ASSIGN	1640	1	1	100.00
CONT_ASSIGN	1641	1	1	100.00
CONT_ASSIGN	1650	1	1	100.00
CONT_ASSIGN	1651	1	1	100.00
CONT_ASSIGN	1652	1	1	100.00
CONT_ASSIGN	1653	1	1	100.00
CONT_ASSIGN	1716	1	1	100.00
CONT_ASSIGN	1718	1	1	100.00
ALWAYS	1723	4	4	100.00
ALWAYS	1732	0	0
ALWAYS	1732	9	9	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1797	1	1	100.00
CONT_ASSIGN	1799	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1807	1	1	100.00
CONT_ASSIGN	1863	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
173	1	1
309	1	1
372	1	1
373	1	1
376	1	1
377	1	1
379	1	1
394	1	1
527	1	1
534	1	1
536	1	1
539	1	1
540	1	1
541	1	1
542	1	1
			MISSING_ELSE
547	1	1
553	1	1
554	1	1
559	1	1
560	1	1
564	1	1
569	1	1
570	1	1
574	1	1
575	1	1
583	1	1
584	1	1
603	1	1
604	1	1
608	1	1
609	1	1
611	1	1
612	1	1
614	1	1
615	1	1
617	1	1
618	1	1
647	1	1
648	1	1
649	1	1
710	1	1
828	2	2
829	1	1
834	1	1
836	1	1
837	1	1
844	1	1
848	1	1
849	1	1
853	1	1
854	1	1
872	1	1
874	1	1
879	1	1
885	1	1
886	1	1
887	1	1
888	1	1
889	1	1
890	1	1
			MISSING_ELSE
896	1	1
897	1	1
898	1	1
899	1	1
901	1	1
903	1	1
905	1	1
907	1	1
911	1	1
913	1	1
914	1	1
915	1	1
918	1	1
920	1	1
921	1	1
922	1	1
927	1	1
929	1	1
930	1	1
931	1	1
935	1	1
937	1	1
938	1	1
939	1	1
964	1	1
965	1	1
1028	1	1
1029	1	1
1030	1	1
1031	1	1
1033	1	1
1034	1	1
1035	1	1
1041	1	1
1042	1	1
1044	1	1
1046	1	1
1047	1	1
1051	1	1
1053	1	1
1054	1	1
1058	1	1
1059	1	1
1060	1	1
1062	1	1
1063	1	1
1078	2	2
1079	1	1
1217	1	1
1220	1	1
1224	1	1
1225	1	1
1226	1	1
1228	1	1
1229	1	1
1232	1	1
1282	0	1
1313	0	1
1396	1	1
1397	1	1
1398	1	1
1399	1	1
1400	1	1
1402	1	1
1406	1	1
1413	1	1
1414	1	1
1416	1	1
1420	1	1
1423	1	1
1426	1	1
1429	1	1
1432	1	1
1435	1	1
1442	1	1
1443	1	1
1482	1	1
1585	0	1
1593	1	1
1594	1	1
1595	1	1
1596	1	1
1597	1	1
1600	1	1
1607	1	1
1614	5	5
1617	1	1
1618	1	1
1619	1	1
1620	1	1
1621	1	1
1622	1	1
1624	1	1
1628	1	1
1630	1	1
1631	1	1
1638	1	1
1640	1	1
1641	1	1
1650	1	1
1651	1	1
1652	1	1
1653	1	1
1716	1	1
1718	1	1
1723	1	1
1724	1	1
1725	1	1
1726	1	1
			MISSING_ELSE
1732	1	1
1733	1	1
1735	1	1
1738	1	1
1739	1	1
1740	1	1
1741	1	1
1743	1	1
1744	1	1
1749	5	5
1750	2	5
1751	3	5
1752	2	5
1754	5	5
1755	5	5
1756	5	5
1797	1	1
1799	1	1
1800	1	1
1801	1	1
1802	1	1
1803	1	1
1805	1	1
1806	1	1
1807	1	1
1863	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       702
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       736
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       858
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       885
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       885
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       885
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       885
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       1044
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T52,T13
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       1217
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       1228
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1229
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1442
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1443
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1607
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       1725
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1797
 EXPRESSION (tpm_rst_in_n | rst_spi_in_n)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T5

 LINE       1863
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T53,T54,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T53,T54,T55

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	63	58	92.06
Total Bits	466	452	97.00
Total Bits 0->1	233	226	97.00
Total Bits 1->0	233	226	97.00

Ports	63	58	92.06
Port Bits	466	452	97.00
Port Bits 0->1	233	226	97.00
Port Bits 1->0	233	226	97.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T13,T14	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T53,T16,T18	Yes	T53,T16,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T53,T16,T18	Yes	T53,T16,T18	OUTPUT
cio_sck_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_csb_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
cio_sd_o[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tpm_csb_i	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T2,*T3,*T5	Yes	T2,T3,T5	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T2,T5,T8	Yes	T2,T3,T5	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T13,T14,T56	Yes	T13,T14,T56	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T13,T15,T56	Yes	T13,T15,T56	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T13,T14,T56	Yes	T13,T14,T56	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.b_ram_lcfg.test	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.a_ram_lcfg.test	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.b_ram_fcfg.test	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T57	Yes	T57	INPUT
ram_cfg_i.a_ram_fcfg.test	Yes	Yes	T57	Yes	T57	INPUT
sck_monitor_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	29	90.62
IF	539	3	3	100.00
IF	828	2	2	100.00
CASE	844	4	4	100.00
IF	885	3	3	100.00
CASE	901	7	5	71.43
IF	1028	2	2	100.00
IF	1044	5	4	80.00
IF	1078	2	2	100.00
IF	1725	2	2	100.00
IF	1735	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	539	if ((!rst_ni))
-2-:	541	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	828	if ((!rst_spi_out_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	844	case (cmd_dp_sel)
-2-:	858	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T2,T3,T4
DpUpload	-	Covered	T2,T4,T5
default	1	Covered	T2,T4,T5
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	885	if (((!sck_csb) && ((spi_mode == FlashMode) || (spi_mode == PassThrough))))
-2-:	888	if (cfg_tpm_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	901	case (spi_mode)
-2-:	903	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T2,T3,T4
FlashMode PassThrough	DpReadStatus	Covered	T2,T4,T5
FlashMode PassThrough	DpReadJEDEC	Covered	T2,T4,T5
FlashMode PassThrough	DpUpload	Covered	T2,T4,T5
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	1028	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1044	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1051	case (spi_mode)
-3-:	1058	if (intercept_en_out)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T5
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T2,T5,T8
0	PassThrough	0	Covered	T2,T3,T5
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1078	if ((!rst_spi_out_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	1725	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1735	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	407295320	407214408	0	0
CioSdoEnOKnown	407295320	407214408	0	0
CioSdoEnOffWhenInactive	407295320	407214408	0	0
FpvSecCmRegWeOnehotCheck_A	407295320	60	0	0
InterceptLevel_M	132036118	0	0	0
IntrReadbufFlipOKnown	407295320	407214408	0	0
IntrReadbufWatermarkOKnown	407295320	407214408	0	0
IntrTpmHeaderNotEmptyOKnown	407295320	407214408	0	0
IntrTpmRdfifoCmdEndOKnown	407295320	407214408	0	0
IntrTpmRdfifoDropOKnown	407295320	407214408	0	0
IntrUploadCmdfifoNotEmptyOKnown	407295320	407214408	0	0
IntrUploadPayloadNotEmptyOKnown	407295320	407214408	0	0
IntrUploadPayloadOverflowOKnown	407295320	407214408	0	0
PayloadStartIdxWidthMatch_A	926	926	0	0
SpiModeKnown_A	407295320	407214408	0	0
TpmEnableWhenTpmCsbIdle_M	407295320	333	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	407295320	1675984	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	407295320	166931	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	407295320	2014	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	407295320	1547	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	407295320	179445	0	0
scanmodeKnown	407295320	407295320	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	60	0	0
T16	3755	10	0	0
T17	562584	0	0	0
T18	0	10	0	0
T21	0	20	0	0
T37	462557	0	0	0
T38	469755	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	59586	0	0	0
T61	63616	0	0	0
T62	778315	0	0	0
T63	865	0	0	0
T64	16398	0	0	0
T65	17218	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132036118	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IntrTpmRdfifoCmdEndOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IntrTpmRdfifoDropOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	333	0	0
T1	177087	1	0	0
T2	417688	1	0	0
T3	46004	0	0	0
T4	347744	0	0	0
T5	270543	2	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	1	0	0
T9	145909	1	0	0
T10	187620	0	0	0
T11	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	1675984	0	0
T2	417688	9152	0	0
T3	46004	832	0	0
T4	347744	9152	0	0
T5	270543	9152	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	8320	0	0
T9	145909	8320	0	0
T10	187620	832	0	0
T11	417869	0	0	0
T12	0	832	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	166931	0	0
T1	177087	201	0	0
T2	417688	1056	0	0
T3	46004	0	0	0
T4	347744	550	0	0
T5	270543	2275	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	1408	0	0
T9	145909	978	0	0
T10	187620	0	0	0
T11	0	380	0	0
T24	0	30	0	0
T26	0	1264	0	0
T27	0	884	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2014	0	0
T2	417688	10	0	0
T3	46004	0	0	0
T4	347744	16	0	0
T5	270543	13	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	8	0	0
T9	145909	11	0	0
T10	187620	0	0	0
T11	417869	0	0	0
T13	0	34	0	0
T26	0	13	0	0
T27	0	13	0	0
T36	0	5	0	0
T40	0	11	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	1547	0	0
T2	417688	6	0	0
T3	46004	0	0	0
T4	347744	13	0	0
T5	270543	9	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	6	0	0
T9	145909	7	0	0
T10	187620	0	0	0
T11	417869	0	0	0
T13	0	30	0	0
T26	0	12	0	0
T27	0	10	0	0
T36	0	2	0	0
T40	0	9	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	179445	0	0
T1	177087	274	0	0
T2	417688	1072	0	0
T3	46004	0	0	0
T4	347744	0	0	0
T5	270543	2878	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	1448	0	0
T9	145909	1578	0	0
T10	187620	0	0	0
T11	0	637	0	0
T24	0	27	0	0
T26	0	1166	0	0
T27	0	851	0	0
T40	0	1099	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407295320	0	0
T1	177087	177087	0	0
T2	417688	417688	0	0
T3	46004	46004	0	0
T4	347744	347744	0	0
T5	270543	270543	0	0
T6	20014	20014	0	0
T7	43541	43541	0	0
T8	144661	144661	0	0
T9	145909	145909	0	0
T10	187620	187620	0	0