Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	511844741	3058078	0	0
DepthKnown_A	511844741	511708616	0	0
RvalidKnown_A	511844741	511708616	0	0
WreadyKnown_A	511844741	511708616	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	3058078	0	0
T2	33136	1663	0	0
T3	25611	832	0	0
T4	102783	1663	0	0
T5	426907	19982	0	0
T6	106459	0	0	0
T7	489286	7484	0	0
T8	159014	0	0	0
T9	1282	0	0	0
T10	5740	0	0	0
T11	24954	1663	0	0
T12	0	1666	0	0
T13	0	6654	0	0
T14	0	832	0	0
T15	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	511844741	3256853	0	0
DepthKnown_A	511844741	511708616	0	0
RvalidKnown_A	511844741	511708616	0	0
WreadyKnown_A	511844741	511708616	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	3256853	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	102783	832	0	0
T5	426907	23567	0	0
T6	106459	0	0	0
T7	489286	4160	0	0
T8	159014	0	0	0
T9	1282	0	0	0
T10	5740	0	0	0
T11	24954	832	0	0
T12	0	835	0	0
T13	0	4992	0	0
T14	0	832	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	511844741	189994	0	0
DepthKnown_A	511844741	511708616	0	0
RvalidKnown_A	511844741	511708616	0	0
WreadyKnown_A	511844741	511708616	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	189994	0	0
T5	426907	644	0	0
T6	106459	648	0	0
T7	489286	420	0	0
T8	159014	157	0	0
T9	1282	0	0	0
T10	5740	18	0	0
T11	24954	0	0	0
T12	320787	0	0	0
T13	167580	256	0	0
T27	7230	16	0	0
T29	0	1223	0	0
T30	0	1463	0	0
T45	0	618	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	511844741	426106	0	0
DepthKnown_A	511844741	511708616	0	0
RvalidKnown_A	511844741	511708616	0	0
WreadyKnown_A	511844741	511708616	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	426106	0	0
T5	426907	2826	0	0
T6	106459	1988	0	0
T7	489286	420	0	0
T8	159014	157	0	0
T9	1282	0	0	0
T10	5740	18	0	0
T11	24954	0	0	0
T12	320787	0	0	0
T13	167580	256	0	0
T27	7230	16	0	0
T29	0	3777	0	0
T30	0	1462	0	0
T45	0	2630	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	511844741	7146235	0	0
DepthKnown_A	511844741	511708616	0	0
RvalidKnown_A	511844741	511708616	0	0
WreadyKnown_A	511844741	511708616	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	7146235	0	0
T1	9216	44	0	0
T2	33136	1285	0	0
T3	25611	637	0	0
T4	102783	4632	0	0
T5	426907	23543	0	0
T6	106459	4130	0	0
T7	489286	8283	0	0
T8	159014	2675	0	0
T9	1282	47	0	0
T10	5740	1271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	511844741	14468989	0	0
DepthKnown_A	511844741	511708616	0	0
RvalidKnown_A	511844741	511708616	0	0
WreadyKnown_A	511844741	511708616	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	14468989	0	0
T1	9216	44	0	0
T2	33136	1284	0	0
T3	25611	637	0	0
T4	102783	19771	0	0
T5	426907	95161	0	0
T6	106459	11966	0	0
T7	489286	8189	0	0
T8	159014	2670	0	0
T9	1282	47	0	0
T10	5740	1271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511844741	511708616	0	0
T1	9216	9149	0	0
T2	33136	33067	0	0
T3	25611	25547	0	0
T4	102783	102705	0	0
T5	426907	426901	0	0
T6	106459	106367	0	0
T7	489286	489191	0	0
T8	159014	158916	0	0
T9	1282	1205	0	0
T10	5740	5646	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0