Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.78	98.41	64.69			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul2sram_egress.u_sramreqfifo	60.67	80.00	31.25			71.43	60.00
tb.dut.u_tlul2sram_egress.u_rspfifo	61.67	86.67	33.33			66.67	60.00
tb.dut.u_upload.u_arbiter.u_req_fifo	62.10	85.71	31.25			71.43	60.00
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo	89.06	100.00	56.25			100.00	100.00
tb.dut.u_sys_sram_arbiter.u_req_fifo	89.06	100.00	56.25			100.00	100.00
tb.dut.u_tlul2sram_ingress.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.u_tlul2sram_egress.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.u_tlul2sram_ingress.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo	93.18	100.00	72.73			100.00	100.00
tb.dut.u_tlul2sram_ingress.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_spi_tpm.u_sram_fifo	94.32	100.00	77.27			100.00	100.00
tb.dut.u_readcmd.u_readsram.u_fifo	95.45	100.00	81.82			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.18	100.00

tb.dut.u_readcmd.u_readsram.u_sram_fifo

SCORE	LINE
94.32	100.00

tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
95.45	100.00

tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
62.10	85.71

tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
89.06	100.00

tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.u_tlul2sram_egress.u_reqfifo

SCORE	LINE
92.19	100.00

tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
60.67	80.00

tb.dut.u_tlul2sram_egress.u_sramreqfifo

SCORE	LINE
90.62	100.00

tb.dut.u_tlul2sram_ingress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
61.67	86.67

tb.dut.u_tlul2sram_egress.u_rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
89.06	100.00

tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
62.10	31.25

tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (3'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.18	72.73

tb.dut.u_readcmd.u_readsram.u_sram_fifo

SCORE	COND
94.32	77.27

tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T7
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
60.67	31.25

tb.dut.u_tlul2sram_egress.u_sramreqfifo

SCORE	COND
90.62	62.50

tb.dut.u_tlul2sram_ingress.u_sramreqfifo

SCORE	COND
89.06	56.25

tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
89.06	56.25

tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (2'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
61.67	33.33

tb.dut.u_tlul2sram_egress.u_rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_tlul2sram_ingress.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T5,T6,T7

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T29
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.19	68.75

tb.dut.u_tlul2sram_egress.u_reqfifo

SCORE	COND
92.19	68.75

tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
95.45	81.82

tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T4,T5,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T7

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
61.67	66.67

tb.dut.u_tlul2sram_egress.u_rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_tlul2sram_ingress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.18	100.00

tb.dut.u_readcmd.u_readsram.u_sram_fifo

SCORE	BRANCH
94.32	100.00

tb.dut.u_spi_tpm.u_sram_fifo

SCORE	BRANCH
95.45	100.00

tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
62.10	71.43

tb.dut.u_upload.u_arbiter.u_req_fifo

SCORE	BRANCH
89.06	100.00

tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

SCORE	BRANCH
92.19	100.00

tb.dut.u_tlul2sram_egress.u_reqfifo

SCORE	BRANCH
92.19	100.00

tb.dut.u_tlul2sram_ingress.u_reqfifo

SCORE	BRANCH
60.67	71.43

tb.dut.u_tlul2sram_egress.u_sramreqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.u_tlul2sram_ingress.u_sramreqfifo

SCORE	BRANCH
89.06	100.00

tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	112183934	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	54934027	0	0
gen_passthru_fifo.paramCheckPass	9208	9208	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	112183934	0	0
T1	36864	88	0	0
T2	231952	7559	0	0
T3	179277	4602	0	0
T4	753173	60518	0	0
T5	5968211	857902	0	0
T6	2436311	19459	0	0
T7	8221806	148707	0	0
T8	2148550	5816	0	0
T9	16666	94	0	0
T10	80924	2596	0	0
T11	312910	45087	0	0
T12	2347626	14601	0	0
T13	2930272	215228	0	0
T14	44670	1664	0	0
T15	0	2495	0	0
T27	46324	16	0	0
T29	0	229633	0	0
T30	0	37706	0	0
T45	0	618	0	0
T49	0	54286	0	0
T50	0	3932	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	140256	139251	0	0
T2	532875	515013	0	0
T3	654005	545109	0	0
T4	1625975	1589571	0	0
T5	6926630	6756763	0	0
T6	2912315	2114561	0	0
T7	9665650	8679282	0	0
T8	2486920	2422220	0	0
T9	19230	18075	0	0
T10	93980	87842	0	0
T11	110405	66243	0	0
T12	317178	317178	0	0
T13	0	1440705	0	0
T14	0	66432	0	0
T15	0	118032	0	0
T27	0	1472	0	0
T28	0	80272	0	0
T29	0	240288	0	0
T30	0	492464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	140256	139251	0	0
T2	532875	515013	0	0
T3	654005	545109	0	0
T4	1625975	1589571	0	0
T5	6926630	6756763	0	0
T6	2912315	2114561	0	0
T7	9665650	8679282	0	0
T8	2486920	2422220	0	0
T9	19230	18075	0	0
T10	93980	87842	0	0
T11	110405	66243	0	0
T12	317178	317178	0	0
T13	0	1440705	0	0
T14	0	66432	0	0
T15	0	118032	0	0
T27	0	1472	0	0
T28	0	80272	0	0
T29	0	240288	0	0
T30	0	492464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	140256	139251	0	0
T2	532875	515013	0	0
T3	654005	545109	0	0
T4	1625975	1589571	0	0
T5	6926630	6756763	0	0
T6	2912315	2114561	0	0
T7	9665650	8679282	0	0
T8	2486920	2422220	0	0
T9	19230	18075	0	0
T10	93980	87842	0	0
T11	110405	66243	0	0
T12	317178	317178	0	0
T13	0	1440705	0	0
T14	0	66432	0	0
T15	0	118032	0	0
T27	0	1472	0	0
T28	0	80272	0	0
T29	0	240288	0	0
T30	0	492464	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	54934027	0	0
T2	33136	832	0	0
T3	25611	832	0	0
T4	136475	31957	0	0
T5	2552955	688999	0	0
T6	1584639	38610	0	0
T7	4307518	127152	0	0
T8	876438	8525	0	0
T9	6410	0	0	0
T10	35004	790	0	0
T11	213094	43424	0	0
T12	1706052	12935	0	0
T13	2595112	209355	0	0
T14	44670	832	0	0
T15	0	832	0	0
T16	0	14382	0	0
T27	31864	128	0	0
T29	0	296759	0	0
T30	0	102102	0	0
T45	0	38996	0	0
T49	0	54286	0	0
T50	0	3932	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	9208	9208	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T5	8	8	0	0
T6	8	8	0	0
T7	8	8	0	0
T8	8	8	0	0
T9	8	8	0	0
T10	8	8	0	0