Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3708838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4269871

1

T1

249

T2

13862

T3

2235

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4419040	1			T1	262		T2	4725		T3	2704
values[0x0]	1779076	1			T1	130		T2	5663		T3	443
values[0x1]	1780593	1			T1	115		T2	5786		T3	450

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2626187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5352522

1

T1

316

T2

14363

T3

2494

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29093	1			T2	97		T3	26		T5	85
valid_sources[0x01]	30759	1			T1	10		T2	83		T3	10
valid_sources[0x02]	29553	1			T2	29		T3	16		T5	63
valid_sources[0x03]	28510	1			T2	48		T3	2		T5	85
valid_sources[0x04]	28859	1			T1	1		T2	48		T3	5
valid_sources[0x05]	28697	1			T2	53		T3	15		T5	69
valid_sources[0x06]	30670	1			T2	74		T3	8		T5	85
valid_sources[0x07]	28605	1			T2	72		T3	11		T5	75
valid_sources[0x08]	28514	1			T2	77		T3	17		T5	56
valid_sources[0x09]	30938	1			T2	66		T3	20		T4	1
valid_sources[0x0a]	30953	1			T2	49		T3	15		T5	82
valid_sources[0x0b]	34436	1			T2	72		T3	19		T5	68
valid_sources[0x0c]	30536	1			T2	62		T3	14		T4	4
valid_sources[0x0d]	27533	1			T2	101		T3	12		T5	103
valid_sources[0x0e]	30657	1			T2	90		T3	26		T4	295
valid_sources[0x0f]	27796	1			T2	66		T3	3		T5	63
valid_sources[0x10]	30139	1			T2	58		T3	19		T5	77
valid_sources[0x11]	27824	1			T2	118		T3	6		T4	1
valid_sources[0x12]	29941	1			T2	55		T3	14		T5	78
valid_sources[0x13]	29373	1			T2	54		T3	18		T4	14
valid_sources[0x14]	29177	1			T2	47		T3	23		T5	66
valid_sources[0x15]	30335	1			T2	38		T3	12		T5	68
valid_sources[0x16]	29090	1			T2	40		T3	17		T5	87
valid_sources[0x17]	27579	1			T2	59		T3	21		T5	66
valid_sources[0x18]	31474	1			T2	119		T3	7		T4	1
valid_sources[0x19]	32107	1			T2	57		T3	22		T5	70
valid_sources[0x1a]	32062	1			T2	43		T3	14		T5	74
valid_sources[0x1b]	29383	1			T2	53		T3	6		T5	73
valid_sources[0x1c]	27912	1			T2	73		T3	13		T5	95
valid_sources[0x1d]	30226	1			T2	58		T3	9		T5	86
valid_sources[0x1e]	31637	1			T2	84		T3	6		T5	77
valid_sources[0x1f]	35685	1			T2	57		T3	11		T5	64
valid_sources[0x20]	33225	1			T2	33		T3	11		T5	73
valid_sources[0x21]	31451	1			T2	51		T3	5		T5	57
valid_sources[0x22]	30671	1			T2	46		T3	27		T5	69
valid_sources[0x23]	32710	1			T2	69		T3	19		T5	77
valid_sources[0x24]	31647	1			T2	67		T3	36		T4	1
valid_sources[0x25]	31232	1			T2	68		T3	12		T4	1
valid_sources[0x26]	29066	1			T2	72		T3	12		T5	73
valid_sources[0x27]	29544	1			T2	63		T3	17		T5	83
valid_sources[0x28]	29809	1			T2	45		T3	19		T5	78
valid_sources[0x29]	33542	1			T2	33		T3	35		T5	73
valid_sources[0x2a]	29375	1			T2	132		T3	17		T5	84
valid_sources[0x2b]	35056	1			T2	60		T3	19		T5	77
valid_sources[0x2c]	31769	1			T2	88		T3	16		T5	75
valid_sources[0x2d]	27059	1			T2	59		T3	10		T5	67
valid_sources[0x2e]	32755	1			T2	68		T3	14		T4	447
valid_sources[0x2f]	32182	1			T2	39		T3	24		T4	1
valid_sources[0x30]	30461	1			T1	4		T2	83		T3	11
valid_sources[0x31]	27932	1			T2	28		T3	13		T5	67
valid_sources[0x32]	28658	1			T1	56		T2	39		T3	9
valid_sources[0x33]	29742	1			T2	68		T3	2		T5	54
valid_sources[0x34]	28674	1			T2	58		T3	32		T5	82
valid_sources[0x35]	56286	1			T2	59		T3	8		T5	72
valid_sources[0x36]	29962	1			T2	89		T3	5		T4	281
valid_sources[0x37]	28462	1			T2	78		T3	6		T5	84
valid_sources[0x38]	31441	1			T2	60		T3	12		T5	81
valid_sources[0x39]	32882	1			T2	78		T3	20		T5	77
valid_sources[0x3a]	27726	1			T2	79		T3	10		T5	79
valid_sources[0x3b]	29611	1			T2	71		T3	29		T5	66
valid_sources[0x3c]	27739	1			T2	81		T3	4		T4	208
valid_sources[0x3d]	32647	1			T2	76		T3	17		T5	81
valid_sources[0x3e]	29286	1			T2	74		T3	17		T5	78
valid_sources[0x3f]	29902	1			T2	74		T3	24		T4	3
valid_sources[0x40]	28265	1			T2	85		T3	4		T5	76
valid_sources[0x41]	28347	1			T2	91		T3	2		T5	90
valid_sources[0x42]	29019	1			T2	68		T3	11		T5	79
valid_sources[0x43]	27748	1			T2	24		T3	2		T5	55
valid_sources[0x44]	66747	1			T2	45		T3	15		T5	62
valid_sources[0x45]	30494	1			T2	60		T3	12		T5	85
valid_sources[0x46]	27448	1			T2	91		T3	12		T5	74
valid_sources[0x47]	30909	1			T2	89		T3	13		T5	75
valid_sources[0x48]	32760	1			T2	36		T3	10		T5	78
valid_sources[0x49]	42742	1			T2	75		T3	22		T5	83
valid_sources[0x4a]	32133	1			T2	68		T3	14		T5	100
valid_sources[0x4b]	33986	1			T2	53		T3	14		T5	70
valid_sources[0x4c]	30883	1			T2	58		T3	16		T5	76
valid_sources[0x4d]	33173	1			T2	50		T3	16		T5	77
valid_sources[0x4e]	31205	1			T2	61		T3	6		T5	85
valid_sources[0x4f]	28869	1			T2	57		T3	12		T5	61
valid_sources[0x50]	31905	1			T2	56		T3	23		T5	81
valid_sources[0x51]	29730	1			T2	97		T3	23		T5	66
valid_sources[0x52]	29965	1			T2	82		T3	10		T5	81
valid_sources[0x53]	29149	1			T2	61		T3	12		T5	69
valid_sources[0x54]	32430	1			T2	38		T3	8		T4	21
valid_sources[0x55]	28549	1			T2	60		T3	14		T5	78
valid_sources[0x56]	33172	1			T2	111		T3	17		T5	59
valid_sources[0x57]	28548	1			T2	78		T3	28		T5	81
valid_sources[0x58]	29843	1			T2	52		T3	7		T4	428
valid_sources[0x59]	31236	1			T2	69		T3	16		T5	70
valid_sources[0x5a]	28859	1			T2	55		T3	19		T5	80
valid_sources[0x5b]	31165	1			T2	72		T3	4		T5	70
valid_sources[0x5c]	34066	1			T2	55		T3	15		T5	48
valid_sources[0x5d]	29650	1			T2	59		T3	7		T4	1
valid_sources[0x5e]	28104	1			T2	94		T3	13		T5	66
valid_sources[0x5f]	32119	1			T2	72		T3	4		T5	78
valid_sources[0x60]	31398	1			T2	94		T3	3		T5	74
valid_sources[0x61]	26954	1			T2	59		T3	3		T5	71
valid_sources[0x62]	27607	1			T2	68		T3	2		T5	81
valid_sources[0x63]	29229	1			T2	71		T3	4		T5	84
valid_sources[0x64]	29094	1			T2	62		T3	20		T5	71
valid_sources[0x65]	29443	1			T2	75		T3	19		T5	71
valid_sources[0x66]	29318	1			T2	83		T3	8		T5	54
valid_sources[0x67]	27689	1			T2	45		T3	20		T5	98
valid_sources[0x68]	28193	1			T2	62		T3	2		T5	85
valid_sources[0x69]	29261	1			T2	37		T3	16		T5	70
valid_sources[0x6a]	27950	1			T2	23		T3	29		T5	71
valid_sources[0x6b]	29047	1			T2	70		T3	16		T5	91
valid_sources[0x6c]	31145	1			T2	56		T3	17		T5	69
valid_sources[0x6d]	29445	1			T2	21		T3	6		T5	85
valid_sources[0x6e]	30634	1			T1	2		T2	60		T3	8
valid_sources[0x6f]	30052	1			T2	62		T3	17		T5	80
valid_sources[0x70]	31049	1			T2	61		T3	20		T5	76
valid_sources[0x71]	31579	1			T2	66		T3	26		T5	74
valid_sources[0x72]	28416	1			T2	50		T3	18		T5	79
valid_sources[0x73]	31135	1			T2	86		T3	22		T5	65
valid_sources[0x74]	27076	1			T2	68		T3	25		T5	84
valid_sources[0x75]	28403	1			T2	75		T3	5		T4	1
valid_sources[0x76]	30088	1			T2	64		T3	5		T5	77
valid_sources[0x77]	30604	1			T2	80		T3	3		T5	60
valid_sources[0x78]	28683	1			T2	76		T3	6		T5	75
valid_sources[0x79]	34816	1			T2	73		T3	24		T5	74
valid_sources[0x7a]	28953	1			T2	55		T3	19		T5	73
valid_sources[0x7b]	29391	1			T2	65		T3	24		T4	82
valid_sources[0x7c]	27389	1			T2	67		T3	12		T5	85
valid_sources[0x7d]	32261	1			T2	73		T3	5		T5	86
valid_sources[0x7e]	32148	1			T2	59		T3	22		T5	66
valid_sources[0x7f]	29621	1			T2	54		T3	26		T5	72
valid_sources[0x80]	28521	1			T2	90		T3	27		T4	86

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1049032

1

T1

74

T2

2467

T3

1355

values[0x0]

all_enables

biggest_size

1621861

1

T1

91

T2

5643

T3

440

values[0x1]

all_enables

biggest_size

1598978

1

T1

84

T2

5752

T3

440