SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_errors_cgs_wrap[spi_device_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 15 | 0 | 15 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_csr_size_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_byte_access_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_ro_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_mem_wo_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tl_protocol_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
cp_unmapped_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_write_w_instr_type_err | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 4510 | 1 | T99 | 1 | T100 | 131 | T101 | 1 | ||||
auto[1] | 1163 | 1 | T100 | 9 | T102 | 2 | T103 | 63 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 4878 | 1 | T99 | 1 | T100 | 112 | T101 | 1 | ||||
auto[1] | 795 | 1 | T100 | 28 | T102 | 3 | T103 | 44 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5214 | 1 | T99 | 1 | T100 | 117 | T101 | 1 | ||||
auto[1] | 459 | 1 | T100 | 23 | T103 | 14 | T105 | 23 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5667 | 1 | T99 | 1 | T100 | 140 | T101 | 1 | ||||
auto[1] | 6 | 1 | T112 | 3 | T116 | 1 | T166 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 4920 | 1 | T99 | 1 | T100 | 99 | T101 | 1 | ||||
auto[1] | 753 | 1 | T100 | 41 | T102 | 1 | T103 | 40 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
covered | 885 | 1 | T102 | 3 | T103 | 78 | T105 | 55 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5483 | 1 | T99 | 1 | T100 | 140 | T101 | 1 | ||||
auto[1] | 190 | 1 | T103 | 11 | T105 | 18 | T111 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 4286 | 1 | T99 | 1 | T100 | 101 | T101 | 1 | ||||
auto[1] | 1387 | 1 | T100 | 39 | T102 | 5 | T103 | 74 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |