Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3733875

1

T1

258

T2

2312

T3

1362

full_word

4269260

1

T1

249

T2

13862

T3

2235

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8002785	1			T1	507		T2	16174		T3	3597
auto[TlIntgErrCmd]	117	1			T99	7		T101	9		T104	4
auto[TlIntgErrData]	117	1			T99	8		T101	13		T104	1
auto[TlIntgErrBoth]	116	1			T99	5		T101	8		T104	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4423647

1

T1

262

T2

4725

T3

2704

auto[1]

3579488

1

T1

245

T2

11449

T3

893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3374177	1			T1	188		T2	2258		T3	1349
auto[TlIntgErrNone]	partial	auto[1]	359375	1			T1	70		T2	54		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	1049309	1			T1	74		T2	2467		T3	1355
auto[TlIntgErrNone]	full_word	auto[1]	3219924	1			T1	175		T2	11395		T3	880
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T99	3		T101	1		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T99	3		T101	8		T104	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T167	1		T172	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T99	1		T173	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T99	5		T101	6		T170	3
auto[TlIntgErrData]	partial	auto[1]	58	1			T99	3		T101	7		T104	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T173	1		T167	2		T175	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T167	1		T176	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T99	2		T101	4		T170	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T99	2		T101	4		T104	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T99	1		T170	1		T171	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T173	1		T168	2		T176	1