Unified Coverage Report :: Module :: spi_p2s

Module : spi_p2s

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.98	100.00	71.43			72.50	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_p2s	85.98	100.00	71.43			72.50	100.00

---

Module Instance : tb.dut.u_p2s

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.98	100.00	71.43			72.50	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.98	100.00	71.43			72.50	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_p2s

	Line No.	Total	Covered	Percent
TOTAL		34	34	100.00
ALWAYS	58	5	5	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	98	5	5	100.00
ALWAYS	110	4	4	100.00
CONT_ASSIGN	130	1	1	100.00
ALWAYS	134	5	5	100.00
CONT_ASSIGN	166	1	1	100.00
ALWAYS	170	6	6	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	183	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
60	1	1
62	1	1
66	1	1
70	1	1
79	1	1
98	1	1
100	1	1
101	1	1
102	1	1
103	1	1
110	1	1
112	1	1
116	1	1
120	1	1
130	1	1
134	1	1
136	1	1
138	1	1
143	1	1
148	1	1
166	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
			MISSING_ELSE
179	1	1
183	1	1
185	1	1
186	1	1
187	1	1
188	1	1

---

Cond Coverage for Module : spi_p2s

	Total	Covered	Percent
Conditions	42	30	71.43
Logical	42	30	71.43
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (csb_i ? 4'b0 : out_enable)
             --1--

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (cnt == 3'h6)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       102
 EXPRESSION (cnt == 3'h2)
            ------1------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       103
 EXPRESSION (cnt == 3'b0)
            ------1------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       112
 EXPRESSION (order_i ? ({1'b0, out_shift_d[7:1]}) : ({out_shift_d[6:0], 1'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       116
 EXPRESSION (order_i ? ({2'b0, out_shift_d[7:2]}) : ({out_shift_d[5:0], 2'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Not Covered

 LINE       120
 EXPRESSION (order_i ? ({4'b0, out_shift_d[7:4]}) : ({out_shift_d[3:0], 4'b0}))
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Not Covered

 LINE       130
 EXPRESSION (first_beat ? data_i : out_shift)
             -----1----

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[0] : data_i[0]) : (((!first_beat)) ? out_shift[7] : data_i[7]))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       138
 SUB-EXPRESSION (((!first_beat)) ? out_shift[0] : data_i[0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7] : data_i[7])
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       143
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[1:0] : data_i[1:0]) : (((!first_beat)) ? out_shift[7:6] : data_i[7:6]))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       143
 SUB-EXPRESSION (((!first_beat)) ? out_shift[1:0] : data_i[1:0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       143
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:6] : data_i[7:6])
                 -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       148
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[3:0] : data_i[3:0]) : (((!first_beat)) ? out_shift[7:4] : data_i[7:4]))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       148
 SUB-EXPRESSION (((!first_beat)) ? out_shift[3:0] : data_i[3:0])
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:4] : data_i[7:4])
                 -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       179
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       186
 EXPRESSION (cnt == 3'('h00000007))
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       187
 EXPRESSION (cnt == 3'('h00000003))
            -----------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

 LINE       188
 EXPRESSION (cnt == 3'('b1))
            --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T3,T5

---

Branch Coverage for Module : spi_p2s

	Line No.	Total	Covered	Percent
Branches		40	29	72.50
TERNARY	79	2	2	100.00
TERNARY	130	2	2	100.00
CASE	60	4	4	100.00
CASE	100	4	3	75.00
CASE	110	7	4	57.14
CASE	136	13	7	53.85
IF	170	4	4	100.00
CASE	185	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	(csb_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	130	(first_beat) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	60	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T1,T2,T3
DualIO	Covered	T1,T2,T3
QuadIO	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	100	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T1,T2,T3
DualIO	Covered	T2,T3,T5
QuadIO	Covered	T2,T3,T5
default	Not Covered

	LineNo.	Expression
-1-:	110	case (io_mode)
-2-:	112	(order_i) ? 
-3-:	116	(order_i) ? 
-4-:	120	(order_i) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
SingleIO	1	-	-	Not Covered
SingleIO	0	-	-	Covered	T1,T2,T3
DualIO	-	1	-	Not Covered
DualIO	-	0	-	Covered	T2,T3,T5
QuadIO	-	-	1	Not Covered
QuadIO	-	-	0	Covered	T2,T3,T5
default	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	case (io_mode)
-2-:	138	(order_i) ? 
-3-:	138	((!first_beat)) ? 
-4-:	138	((!first_beat)) ? 
-5-:	143	(order_i) ? 
-6-:	143	((!first_beat)) ? 
-7-:	143	((!first_beat)) ? 
-8-:	148	(order_i) ? 
-9-:	148	((!first_beat)) ? 
-10-:	148	((!first_beat)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
SingleIO	1	1	-	-	-	-	-	-	-	Not Covered
SingleIO	1	0	-	-	-	-	-	-	-	Not Covered
SingleIO	0	-	1	-	-	-	-	-	-	Covered	T2,T3,T5
SingleIO	0	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
DualIO	-	-	-	1	1	-	-	-	-	Not Covered
DualIO	-	-	-	1	0	-	-	-	-	Not Covered
DualIO	-	-	-	0	-	1	-	-	-	Covered	T2,T3,T5
DualIO	-	-	-	0	-	0	-	-	-	Covered	T2,T3,T5
QuadIO	-	-	-	-	-	-	1	1	-	Not Covered
QuadIO	-	-	-	-	-	-	1	0	-	Not Covered
QuadIO	-	-	-	-	-	-	0	-	1	Covered	T2,T3,T5
QuadIO	-	-	-	-	-	-	0	-	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	if ((!rst_ni))
-2-:	172	if (last_beat)
-3-:	174	if (data_valid_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	185	case (io_mode)

Branches:

-1-	Status	Tests
SingleIO	Covered	T1,T2,T3
DualIO	Covered	T2,T3,T5
QuadIO	Covered	T2,T3,T5
default	Not Covered

---

Assert Coverage for Module : spi_p2s

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoModeChangeValid_A	143057040	7175	0	0
IoModeDefault_A	143057040	19988	0	0

IoModeChangeValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143057040	7175	0	0
T2	465281	21	0	0
T3	17495	10	0	0
T4	65832	0	0	0
T5	775395	31	0	0
T6	1	0	0	0
T7	66400	1	0	0
T8	1	0	0	0
T9	29407	0	0	0
T10	15577	9	0	0
T11	178389	0	0	0
T13	0	1	0	0
T14	0	17	0	0
T15	0	69	0	0
T16	0	9	0	0
T17	0	5	0	0

IoModeDefault_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143057040	19988	0	0
T2	465281	17	0	0
T3	17495	1	0	0
T4	65832	0	0	0
T5	775395	224	0	0
T6	1	0	0	0
T7	66400	2	0	0
T8	1	0	0	0
T9	29407	0	0	0
T10	15577	3	0	0
T11	178389	0	0	0
T13	0	2	0	0
T14	0	123	0	0
T15	0	14	0	0
T16	0	6	0	0
T17	0	2	0	0