Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473708879	2868662	0	0
DepthKnown_A	473708879	473581683	0	0
RvalidKnown_A	473708879	473581683	0	0
WreadyKnown_A	473708879	473581683	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	2868662	0	0
T2	288006	18340	0	0
T3	90916	832	0	0
T4	276548	0	0	0
T5	422250	10812	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	1666	0	0
T11	196091	0	0	0
T13	0	1663	0	0
T14	0	4991	0	0
T15	0	17488	0	0
T16	0	4991	0	0
T40	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473708879	3145006	0	0
DepthKnown_A	473708879	473581683	0	0
RvalidKnown_A	473708879	473581683	0	0
WreadyKnown_A	473708879	473581683	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	3145006	0	0
T2	288006	22886	0	0
T3	90916	832	0	0
T4	276548	0	0	0
T5	422250	7488	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	837	0	0
T11	196091	0	0	0
T13	0	832	0	0
T14	0	4160	0	0
T15	0	32311	0	0
T16	0	4160	0	0
T40	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473708879	194047	0	0
DepthKnown_A	473708879	473581683	0	0
RvalidKnown_A	473708879	473581683	0	0
WreadyKnown_A	473708879	473581683	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	194047	0	0
T1	16601	57	0	0
T2	288006	358	0	0
T3	90916	0	0	0
T4	276548	525	0	0
T5	422250	989	0	0
T6	959	0	0	0
T7	75714	0	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	0	0	0
T11	0	902	0	0
T12	0	24	0	0
T14	0	649	0	0
T15	0	288	0	0
T16	0	64	0	0
T24	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473708879	407534	0	0
DepthKnown_A	473708879	473581683	0	0
RvalidKnown_A	473708879	473581683	0	0
WreadyKnown_A	473708879	473581683	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	407534	0	0
T1	16601	222	0	0
T2	288006	1730	0	0
T3	90916	0	0	0
T4	276548	525	0	0
T5	422250	986	0	0
T6	959	0	0	0
T7	75714	0	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	0	0	0
T11	0	4023	0	0
T12	0	118	0	0
T14	0	649	0	0
T15	0	1297	0	0
T16	0	64	0	0
T24	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473708879	6350194	0	0
DepthKnown_A	473708879	473581683	0	0
RvalidKnown_A	473708879	473581683	0	0
WreadyKnown_A	473708879	473581683	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	6350194	0	0
T1	16601	515	0	0
T2	288006	5040	0	0
T3	90916	2767	0	0
T4	276548	5546	0	0
T5	422250	10569	0	0
T6	959	3	0	0
T7	75714	148	0	0
T8	1138	3	0	0
T9	15121	78	0	0
T10	113823	408	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473708879	12744741	0	0
DepthKnown_A	473708879	473581683	0	0
RvalidKnown_A	473708879	473581683	0	0
WreadyKnown_A	473708879	473581683	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	12744741	0	0
T1	16601	1997	0	0
T2	288006	21739	0	0
T3	90916	2765	0	0
T4	276548	5529	0	0
T5	422250	10470	0	0
T6	959	3	0	0
T7	75714	148	0	0
T8	1138	3	0	0
T9	15121	78	0	0
T10	113823	1836	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473708879	473581683	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0