Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T14
1	0	Covered	T2,T5,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T2,T5,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	757420300	612984028	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	757420300	3751081	0	0
GntImpliesValid_A	757420300	3751081	0	0
GrantKnown_A	757420300	612984028	0	0
IdxKnown_A	757420300	612984028	0	0
IndexIsCorrect_A	757420300	3751081	0	0
LockArbDecision_A	757420300	0	0	0
NoReadyValidNoGrant_A	757420300	0	0	0
ReadyAndValidImplyGrant_A	757420300	3751081	0	0
ReqAndReadyImplyGrant_A	757420300	3751081	0	0
ReqImpliesValid_A	757420300	3751081	0	0
ReqStaysHighUntilGranted0_M	757420300	0	0	0
RoundRobin_A	757420300	6	0	974
ValidKnown_A	757420300	612984028	0	0
gen_data_port_assertion.DataFlow_A	757420300	3751081	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	612984028	0	0
T1	28625	27888	0	0
T2	1218566	749772	0	0
T3	125904	108339	0	0
T4	408210	338878	0	0
T5	1973038	1191542	0	0
T6	959	876	0	0
T7	208512	141969	0	0
T8	1138	1067	0	0
T9	73933	42852	0	0
T10	144975	129080	0	0
T11	356776	172912	0	0
T12	5888	2944	0	0
T13	17661	17488	0	0
T14	0	401412	0	0
T15	0	102169	0	0
T16	0	237438	0	0
T17	0	34224	0	0
T26	0	45136	0	0
T28	0	2488	0	0
T29	0	37912	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	3751081	0	0
T1	28625	451	0	0
T2	1218566	14202	0	0
T3	125904	832	0	0
T4	408210	4250	0	0
T5	1973038	20136	0	0
T6	959	0	0	0
T7	208512	832	0	0
T8	1138	0	0	0
T9	73933	0	0	0
T10	144975	832	0	0
T11	356776	6720	0	0
T12	5888	193	0	0
T13	17661	0	0	0
T14	0	6498	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	7990	0	0
T28	0	159	0	0
T29	0	11741	0	0
T40	0	832	0	0
T43	0	72	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	3751081	0	0
T1	28625	451	0	0
T2	1218566	14202	0	0
T3	125904	832	0	0
T4	408210	4250	0	0
T5	1973038	20136	0	0
T6	959	0	0	0
T7	208512	832	0	0
T8	1138	0	0	0
T9	73933	0	0	0
T10	144975	832	0	0
T11	356776	6720	0	0
T12	5888	193	0	0
T13	17661	0	0	0
T14	0	6498	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	7990	0	0
T28	0	159	0	0
T29	0	11741	0	0
T40	0	832	0	0
T43	0	72	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	612984028	0	0
T1	28625	27888	0	0
T2	1218566	749772	0	0
T3	125904	108339	0	0
T4	408210	338878	0	0
T5	1973038	1191542	0	0
T6	959	876	0	0
T7	208512	141969	0	0
T8	1138	1067	0	0
T9	73933	42852	0	0
T10	144975	129080	0	0
T11	356776	172912	0	0
T12	5888	2944	0	0
T13	17661	17488	0	0
T14	0	401412	0	0
T15	0	102169	0	0
T16	0	237438	0	0
T17	0	34224	0	0
T26	0	45136	0	0
T28	0	2488	0	0
T29	0	37912	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	612984028	0	0
T1	28625	27888	0	0
T2	1218566	749772	0	0
T3	125904	108339	0	0
T4	408210	338878	0	0
T5	1973038	1191542	0	0
T6	959	876	0	0
T7	208512	141969	0	0
T8	1138	1067	0	0
T9	73933	42852	0	0
T10	144975	129080	0	0
T11	356776	172912	0	0
T12	5888	2944	0	0
T13	17661	17488	0	0
T14	0	401412	0	0
T15	0	102169	0	0
T16	0	237438	0	0
T17	0	34224	0	0
T26	0	45136	0	0
T28	0	2488	0	0
T29	0	37912	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	3751081	0	0
T1	28625	451	0	0
T2	1218566	14202	0	0
T3	125904	832	0	0
T4	408210	4250	0	0
T5	1973038	20136	0	0
T6	959	0	0	0
T7	208512	832	0	0
T8	1138	0	0	0
T9	73933	0	0	0
T10	144975	832	0	0
T11	356776	6720	0	0
T12	5888	193	0	0
T13	17661	0	0	0
T14	0	6498	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	7990	0	0
T28	0	159	0	0
T29	0	11741	0	0
T40	0	832	0	0
T43	0	72	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	3751081	0	0
T1	28625	451	0	0
T2	1218566	14202	0	0
T3	125904	832	0	0
T4	408210	4250	0	0
T5	1973038	20136	0	0
T6	959	0	0	0
T7	208512	832	0	0
T8	1138	0	0	0
T9	73933	0	0	0
T10	144975	832	0	0
T11	356776	6720	0	0
T12	5888	193	0	0
T13	17661	0	0	0
T14	0	6498	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	7990	0	0
T28	0	159	0	0
T29	0	11741	0	0
T40	0	832	0	0
T43	0	72	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	3751081	0	0
T1	28625	451	0	0
T2	1218566	14202	0	0
T3	125904	832	0	0
T4	408210	4250	0	0
T5	1973038	20136	0	0
T6	959	0	0	0
T7	208512	832	0	0
T8	1138	0	0	0
T9	73933	0	0	0
T10	144975	832	0	0
T11	356776	6720	0	0
T12	5888	193	0	0
T13	17661	0	0	0
T14	0	6498	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	7990	0	0
T28	0	159	0	0
T29	0	11741	0	0
T40	0	832	0	0
T43	0	72	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	3751081	0	0
T1	28625	451	0	0
T2	1218566	14202	0	0
T3	125904	832	0	0
T4	408210	4250	0	0
T5	1973038	20136	0	0
T6	959	0	0	0
T7	208512	832	0	0
T8	1138	0	0	0
T9	73933	0	0	0
T10	144975	832	0	0
T11	356776	6720	0	0
T12	5888	193	0	0
T13	17661	0	0	0
T14	0	6498	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	7990	0	0
T28	0	159	0	0
T29	0	11741	0	0
T40	0	832	0	0
T43	0	72	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	6	0	974
T20	158182	0	0	1
T32	0	1	0	0
T39	826913	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	2525	0	0	1
T52	15813	0	0	1
T53	7172	0	0	1
T54	14693	0	0	1
T55	1523	0	0	1
T56	33537	0	0	1
T57	5087	0	0	1
T58	216331	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	612984028	0	0
T1	28625	27888	0	0
T2	1218566	749772	0	0
T3	125904	108339	0	0
T4	408210	338878	0	0
T5	1973038	1191542	0	0
T6	959	876	0	0
T7	208512	141969	0	0
T8	1138	1067	0	0
T9	73933	42852	0	0
T10	144975	129080	0	0
T11	356776	172912	0	0
T12	5888	2944	0	0
T13	17661	17488	0	0
T14	0	401412	0	0
T15	0	102169	0	0
T16	0	237438	0	0
T17	0	34224	0	0
T26	0	45136	0	0
T28	0	2488	0	0
T29	0	37912	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757420300	3751081	0	0
T1	28625	451	0	0
T2	1218566	14202	0	0
T3	125904	832	0	0
T4	408210	4250	0	0
T5	1973038	20136	0	0
T6	959	0	0	0
T7	208512	832	0	0
T8	1138	0	0	0
T9	73933	0	0	0
T10	144975	832	0	0
T11	356776	6720	0	0
T12	5888	193	0	0
T13	17661	0	0	0
T14	0	6498	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	7990	0	0
T28	0	159	0	0
T29	0	11741	0	0
T40	0	832	0	0
T43	0	72	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143056086	27584760	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	143056086	620773	0	0
GntImpliesValid_A	143056086	620773	0	0
GrantKnown_A	143056086	27584760	0	0
IdxKnown_A	143056086	27584760	0	0
IndexIsCorrect_A	143056086	620773	0	0
LockArbDecision_A	143056086	0	0	0
NoReadyValidNoGrant_A	143056086	0	0	0
ReadyAndValidImplyGrant_A	143056086	620773	0	0
ReqAndReadyImplyGrant_A	143056086	620773	0	0
ReqImpliesValid_A	143056086	620773	0	0
ReqStaysHighUntilGranted0_M	143056086	0	0	0
RoundRobin_A	143056086	0	0	0
ValidKnown_A	143056086	27584760	0	0
gen_data_port_assertion.DataFlow_A	143056086	620773	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	27584760	0	0
T1	12024	11368	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	62424	0	0
T5	775394	235768	0	0
T7	66399	0	0	0
T9	29406	27824	0	0
T10	15576	0	0	0
T11	178388	172912	0	0
T12	2944	2944	0	0
T14	0	104768	0	0
T26	0	45136	0	0
T28	0	2488	0	0
T29	0	37912	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	620773	0	0
T1	12024	309	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	2923	0	0
T5	775394	3630	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	4724	0	0
T12	2944	129	0	0
T14	0	2653	0	0
T26	0	1716	0	0
T28	0	159	0	0
T29	0	1631	0	0
T43	0	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	620773	0	0
T1	12024	309	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	2923	0	0
T5	775394	3630	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	4724	0	0
T12	2944	129	0	0
T14	0	2653	0	0
T26	0	1716	0	0
T28	0	159	0	0
T29	0	1631	0	0
T43	0	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	27584760	0	0
T1	12024	11368	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	62424	0	0
T5	775394	235768	0	0
T7	66399	0	0	0
T9	29406	27824	0	0
T10	15576	0	0	0
T11	178388	172912	0	0
T12	2944	2944	0	0
T14	0	104768	0	0
T26	0	45136	0	0
T28	0	2488	0	0
T29	0	37912	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	27584760	0	0
T1	12024	11368	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	62424	0	0
T5	775394	235768	0	0
T7	66399	0	0	0
T9	29406	27824	0	0
T10	15576	0	0	0
T11	178388	172912	0	0
T12	2944	2944	0	0
T14	0	104768	0	0
T26	0	45136	0	0
T28	0	2488	0	0
T29	0	37912	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	620773	0	0
T1	12024	309	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	2923	0	0
T5	775394	3630	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	4724	0	0
T12	2944	129	0	0
T14	0	2653	0	0
T26	0	1716	0	0
T28	0	159	0	0
T29	0	1631	0	0
T43	0	72	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	620773	0	0
T1	12024	309	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	2923	0	0
T5	775394	3630	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	4724	0	0
T12	2944	129	0	0
T14	0	2653	0	0
T26	0	1716	0	0
T28	0	159	0	0
T29	0	1631	0	0
T43	0	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	620773	0	0
T1	12024	309	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	2923	0	0
T5	775394	3630	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	4724	0	0
T12	2944	129	0	0
T14	0	2653	0	0
T26	0	1716	0	0
T28	0	159	0	0
T29	0	1631	0	0
T43	0	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	620773	0	0
T1	12024	309	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	2923	0	0
T5	775394	3630	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	4724	0	0
T12	2944	129	0	0
T14	0	2653	0	0
T26	0	1716	0	0
T28	0	159	0	0
T29	0	1631	0	0
T43	0	72	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	27584760	0	0
T1	12024	11368	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	62424	0	0
T5	775394	235768	0	0
T7	66399	0	0	0
T9	29406	27824	0	0
T10	15576	0	0	0
T11	178388	172912	0	0
T12	2944	2944	0	0
T14	0	104768	0	0
T26	0	45136	0	0
T28	0	2488	0	0
T29	0	37912	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	620773	0	0
T1	12024	309	0	0
T2	465280	0	0	0
T3	17494	0	0	0
T4	65831	2923	0	0
T5	775394	3630	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	4724	0	0
T12	2944	129	0	0
T14	0	2653	0	0
T26	0	1716	0	0
T28	0	159	0	0
T29	0	1631	0	0
T43	0	72	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T14
1	0	Covered	T2,T5,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T2,T5,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T14
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143056086	114177154	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	143056086	884613	0	0
GntImpliesValid_A	143056086	884613	0	0
GrantKnown_A	143056086	114177154	0	0
IdxKnown_A	143056086	114177154	0	0
IndexIsCorrect_A	143056086	884613	0	0
LockArbDecision_A	143056086	0	0	0
NoReadyValidNoGrant_A	143056086	0	0	0
ReadyAndValidImplyGrant_A	143056086	884613	0	0
ReqAndReadyImplyGrant_A	143056086	884613	0	0
ReqImpliesValid_A	143056086	884613	0	0
ReqStaysHighUntilGranted0_M	143056086	0	0	0
RoundRobin_A	143056086	0	0	0
ValidKnown_A	143056086	114177154	0	0
gen_data_port_assertion.DataFlow_A	143056086	884613	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	114177154	0	0
T2	465280	461775	0	0
T3	17494	17494	0	0
T4	65831	0	0	0
T5	775394	533615	0	0
T7	66399	66320	0	0
T9	29406	0	0	0
T10	15576	15314	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	17488	0	0
T14	0	296644	0	0
T15	0	102169	0	0
T16	0	237438	0	0
T17	0	34224	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	884613	0	0
T2	465280	2993	0	0
T3	17494	0	0	0
T4	65831	0	0	0
T5	775394	6709	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	0	0	0
T14	0	3845	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	6274	0	0
T29	0	10110	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	884613	0	0
T2	465280	2993	0	0
T3	17494	0	0	0
T4	65831	0	0	0
T5	775394	6709	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	0	0	0
T14	0	3845	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	6274	0	0
T29	0	10110	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	114177154	0	0
T2	465280	461775	0	0
T3	17494	17494	0	0
T4	65831	0	0	0
T5	775394	533615	0	0
T7	66399	66320	0	0
T9	29406	0	0	0
T10	15576	15314	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	17488	0	0
T14	0	296644	0	0
T15	0	102169	0	0
T16	0	237438	0	0
T17	0	34224	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	114177154	0	0
T2	465280	461775	0	0
T3	17494	17494	0	0
T4	65831	0	0	0
T5	775394	533615	0	0
T7	66399	66320	0	0
T9	29406	0	0	0
T10	15576	15314	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	17488	0	0
T14	0	296644	0	0
T15	0	102169	0	0
T16	0	237438	0	0
T17	0	34224	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	884613	0	0
T2	465280	2993	0	0
T3	17494	0	0	0
T4	65831	0	0	0
T5	775394	6709	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	0	0	0
T14	0	3845	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	6274	0	0
T29	0	10110	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	884613	0	0
T2	465280	2993	0	0
T3	17494	0	0	0
T4	65831	0	0	0
T5	775394	6709	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	0	0	0
T14	0	3845	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	6274	0	0
T29	0	10110	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	884613	0	0
T2	465280	2993	0	0
T3	17494	0	0	0
T4	65831	0	0	0
T5	775394	6709	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	0	0	0
T14	0	3845	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	6274	0	0
T29	0	10110	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	884613	0	0
T2	465280	2993	0	0
T3	17494	0	0	0
T4	65831	0	0	0
T5	775394	6709	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	0	0	0
T14	0	3845	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	6274	0	0
T29	0	10110	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	114177154	0	0
T2	465280	461775	0	0
T3	17494	17494	0	0
T4	65831	0	0	0
T5	775394	533615	0	0
T7	66399	66320	0	0
T9	29406	0	0	0
T10	15576	15314	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	17488	0	0
T14	0	296644	0	0
T15	0	102169	0	0
T16	0	237438	0	0
T17	0	34224	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143056086	884613	0	0
T2	465280	2993	0	0
T3	17494	0	0	0
T4	65831	0	0	0
T5	775394	6709	0	0
T7	66399	0	0	0
T9	29406	0	0	0
T10	15576	0	0	0
T11	178388	0	0	0
T12	2944	0	0	0
T13	17661	0	0	0
T14	0	3845	0	0
T15	0	3878	0	0
T16	0	880	0	0
T26	0	6274	0	0
T29	0	10110	0	0
T44	0	1448	0	0
T45	0	3646	0	0
T46	0	3578	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	471308128	471222114	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	471308128	2245695	0	0
GntImpliesValid_A	471308128	2245695	0	0
GrantKnown_A	471308128	471222114	0	0
IdxKnown_A	471308128	471222114	0	0
IndexIsCorrect_A	471308128	2245695	0	0
LockArbDecision_A	471308128	0	0	0
NoReadyValidNoGrant_A	471308128	0	0	0
ReadyAndValidImplyGrant_A	471308128	2245695	0	0
ReqAndReadyImplyGrant_A	471308128	2245695	0	0
ReqImpliesValid_A	471308128	2245695	0	0
ReqStaysHighUntilGranted0_M	471308128	0	0	0
RoundRobin_A	471308128	6	0	974
ValidKnown_A	471308128	471222114	0	0
gen_data_port_assertion.DataFlow_A	471308128	2245695	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	471222114	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	2245695	0	0
T1	16601	142	0	0
T2	288006	11209	0	0
T3	90916	832	0	0
T4	276548	1327	0	0
T5	422250	9797	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	832	0	0
T11	0	1996	0	0
T12	0	64	0	0
T40	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	2245695	0	0
T1	16601	142	0	0
T2	288006	11209	0	0
T3	90916	832	0	0
T4	276548	1327	0	0
T5	422250	9797	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	832	0	0
T11	0	1996	0	0
T12	0	64	0	0
T40	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	471222114	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	471222114	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	2245695	0	0
T1	16601	142	0	0
T2	288006	11209	0	0
T3	90916	832	0	0
T4	276548	1327	0	0
T5	422250	9797	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	832	0	0
T11	0	1996	0	0
T12	0	64	0	0
T40	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	2245695	0	0
T1	16601	142	0	0
T2	288006	11209	0	0
T3	90916	832	0	0
T4	276548	1327	0	0
T5	422250	9797	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	832	0	0
T11	0	1996	0	0
T12	0	64	0	0
T40	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	2245695	0	0
T1	16601	142	0	0
T2	288006	11209	0	0
T3	90916	832	0	0
T4	276548	1327	0	0
T5	422250	9797	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	832	0	0
T11	0	1996	0	0
T12	0	64	0	0
T40	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	2245695	0	0
T1	16601	142	0	0
T2	288006	11209	0	0
T3	90916	832	0	0
T4	276548	1327	0	0
T5	422250	9797	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	832	0	0
T11	0	1996	0	0
T12	0	64	0	0
T40	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	6	0	974
T20	158182	0	0	1
T32	0	1	0	0
T39	826913	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	2525	0	0	1
T52	15813	0	0	1
T53	7172	0	0	1
T54	14693	0	0	1
T55	1523	0	0	1
T56	33537	0	0	1
T57	5087	0	0	1
T58	216331	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	471222114	0	0
T1	16601	16520	0	0
T2	288006	287997	0	0
T3	90916	90845	0	0
T4	276548	276454	0	0
T5	422250	422159	0	0
T6	959	876	0	0
T7	75714	75649	0	0
T8	1138	1067	0	0
T9	15121	15028	0	0
T10	113823	113766	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471308128	2245695	0	0
T1	16601	142	0	0
T2	288006	11209	0	0
T3	90916	832	0	0
T4	276548	1327	0	0
T5	422250	9797	0	0
T6	959	0	0	0
T7	75714	832	0	0
T8	1138	0	0	0
T9	15121	0	0	0
T10	113823	832	0	0
T11	0	1996	0	0
T12	0	64	0	0
T40	0	832	0	0