Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
4008 | 
0 | 
0 | 
| T99 | 
67142 | 
3 | 
0 | 
0 | 
| T100 | 
2976 | 
65 | 
0 | 
0 | 
| T101 | 
108165 | 
4 | 
0 | 
0 | 
| T102 | 
5583 | 
5 | 
0 | 
0 | 
| T103 | 
6284 | 
259 | 
0 | 
0 | 
| T105 | 
6756 | 
234 | 
0 | 
0 | 
| T110 | 
3482 | 
80 | 
0 | 
0 | 
| T115 | 
14426 | 
7 | 
0 | 
0 | 
| T117 | 
15404 | 
5 | 
0 | 
0 | 
| T118 | 
8592 | 
6 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2663 | 
0 | 
0 | 
| T80 | 
3352 | 
14 | 
0 | 
0 | 
| T99 | 
67142 | 
56 | 
0 | 
0 | 
| T101 | 
108165 | 
99 | 
0 | 
0 | 
| T115 | 
14426 | 
33 | 
0 | 
0 | 
| T117 | 
15404 | 
22 | 
0 | 
0 | 
| T120 | 
9219 | 
10 | 
0 | 
0 | 
| T124 | 
10057 | 
3 | 
0 | 
0 | 
| T128 | 
10742 | 
7 | 
0 | 
0 | 
| T129 | 
78860 | 
118 | 
0 | 
0 | 
| T155 | 
41578 | 
273 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2717 | 
0 | 
0 | 
| T80 | 
3352 | 
10 | 
0 | 
0 | 
| T99 | 
67142 | 
79 | 
0 | 
0 | 
| T101 | 
108165 | 
106 | 
0 | 
0 | 
| T115 | 
14426 | 
25 | 
0 | 
0 | 
| T117 | 
15404 | 
30 | 
0 | 
0 | 
| T120 | 
9219 | 
9 | 
0 | 
0 | 
| T124 | 
10057 | 
5 | 
0 | 
0 | 
| T128 | 
10742 | 
15 | 
0 | 
0 | 
| T129 | 
78860 | 
143 | 
0 | 
0 | 
| T155 | 
41578 | 
272 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
3484 | 
0 | 
0 | 
| T80 | 
3352 | 
11 | 
0 | 
0 | 
| T99 | 
67142 | 
122 | 
0 | 
0 | 
| T101 | 
108165 | 
260 | 
0 | 
0 | 
| T115 | 
14426 | 
36 | 
0 | 
0 | 
| T117 | 
15404 | 
22 | 
0 | 
0 | 
| T120 | 
9219 | 
13 | 
0 | 
0 | 
| T124 | 
10057 | 
25 | 
0 | 
0 | 
| T128 | 
10742 | 
21 | 
0 | 
0 | 
| T129 | 
78860 | 
182 | 
0 | 
0 | 
| T155 | 
41578 | 
261 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
11939 | 
0 | 
0 | 
| T80 | 
3352 | 
5 | 
0 | 
0 | 
| T99 | 
67142 | 
1452 | 
0 | 
0 | 
| T101 | 
108165 | 
1973 | 
0 | 
0 | 
| T115 | 
14426 | 
242 | 
0 | 
0 | 
| T117 | 
15404 | 
250 | 
0 | 
0 | 
| T120 | 
9219 | 
152 | 
0 | 
0 | 
| T124 | 
10057 | 
140 | 
0 | 
0 | 
| T128 | 
10742 | 
150 | 
0 | 
0 | 
| T129 | 
78860 | 
140 | 
0 | 
0 | 
| T155 | 
41578 | 
254 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
11189 | 
0 | 
0 | 
| T80 | 
3352 | 
10 | 
0 | 
0 | 
| T99 | 
67142 | 
1069 | 
0 | 
0 | 
| T101 | 
108165 | 
1839 | 
0 | 
0 | 
| T115 | 
14426 | 
311 | 
0 | 
0 | 
| T117 | 
15404 | 
135 | 
0 | 
0 | 
| T120 | 
9219 | 
85 | 
0 | 
0 | 
| T124 | 
10057 | 
243 | 
0 | 
0 | 
| T128 | 
10742 | 
147 | 
0 | 
0 | 
| T129 | 
78860 | 
136 | 
0 | 
0 | 
| T155 | 
41578 | 
293 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
12632 | 
0 | 
0 | 
| T80 | 
3352 | 
10 | 
0 | 
0 | 
| T99 | 
67142 | 
1426 | 
0 | 
0 | 
| T101 | 
108165 | 
2259 | 
0 | 
0 | 
| T115 | 
14426 | 
270 | 
0 | 
0 | 
| T117 | 
15404 | 
413 | 
0 | 
0 | 
| T120 | 
9219 | 
277 | 
0 | 
0 | 
| T124 | 
10057 | 
262 | 
0 | 
0 | 
| T128 | 
10742 | 
263 | 
0 | 
0 | 
| T129 | 
78860 | 
138 | 
0 | 
0 | 
| T155 | 
41578 | 
214 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
12293 | 
0 | 
0 | 
| T80 | 
3352 | 
8 | 
0 | 
0 | 
| T99 | 
67142 | 
1513 | 
0 | 
0 | 
| T101 | 
108165 | 
1928 | 
0 | 
0 | 
| T115 | 
14426 | 
17 | 
0 | 
0 | 
| T117 | 
15404 | 
283 | 
0 | 
0 | 
| T120 | 
9219 | 
245 | 
0 | 
0 | 
| T124 | 
10057 | 
286 | 
0 | 
0 | 
| T128 | 
10742 | 
125 | 
0 | 
0 | 
| T129 | 
78860 | 
99 | 
0 | 
0 | 
| T155 | 
41578 | 
262 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
11604 | 
0 | 
0 | 
| T80 | 
3352 | 
4 | 
0 | 
0 | 
| T99 | 
67142 | 
1132 | 
0 | 
0 | 
| T101 | 
108165 | 
1764 | 
0 | 
0 | 
| T115 | 
14426 | 
248 | 
0 | 
0 | 
| T117 | 
15404 | 
135 | 
0 | 
0 | 
| T120 | 
9219 | 
235 | 
0 | 
0 | 
| T124 | 
10057 | 
125 | 
0 | 
0 | 
| T128 | 
10742 | 
84 | 
0 | 
0 | 
| T129 | 
78860 | 
167 | 
0 | 
0 | 
| T155 | 
41578 | 
256 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
10951 | 
0 | 
0 | 
| T80 | 
3352 | 
5 | 
0 | 
0 | 
| T99 | 
67142 | 
739 | 
0 | 
0 | 
| T101 | 
108165 | 
1853 | 
0 | 
0 | 
| T115 | 
14426 | 
264 | 
0 | 
0 | 
| T117 | 
15404 | 
296 | 
0 | 
0 | 
| T120 | 
9219 | 
116 | 
0 | 
0 | 
| T124 | 
10057 | 
10 | 
0 | 
0 | 
| T128 | 
10742 | 
341 | 
0 | 
0 | 
| T129 | 
78860 | 
128 | 
0 | 
0 | 
| T155 | 
41578 | 
255 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
11108 | 
0 | 
0 | 
| T80 | 
3352 | 
7 | 
0 | 
0 | 
| T99 | 
67142 | 
1102 | 
0 | 
0 | 
| T101 | 
108165 | 
2036 | 
0 | 
0 | 
| T115 | 
14426 | 
214 | 
0 | 
0 | 
| T117 | 
15404 | 
167 | 
0 | 
0 | 
| T120 | 
9219 | 
224 | 
0 | 
0 | 
| T124 | 
10057 | 
149 | 
0 | 
0 | 
| T128 | 
10742 | 
15 | 
0 | 
0 | 
| T129 | 
78860 | 
164 | 
0 | 
0 | 
| T155 | 
41578 | 
238 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
12374 | 
0 | 
0 | 
| T99 | 
67142 | 
1352 | 
0 | 
0 | 
| T101 | 
108165 | 
1916 | 
0 | 
0 | 
| T115 | 
14426 | 
164 | 
0 | 
0 | 
| T117 | 
15404 | 
146 | 
0 | 
0 | 
| T120 | 
9219 | 
15 | 
0 | 
0 | 
| T124 | 
10057 | 
246 | 
0 | 
0 | 
| T128 | 
10742 | 
218 | 
0 | 
0 | 
| T129 | 
78860 | 
163 | 
0 | 
0 | 
| T155 | 
41578 | 
255 | 
0 | 
0 | 
| T156 | 
13827 | 
55 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6177 | 
0 | 
0 | 
| T80 | 
3352 | 
5 | 
0 | 
0 | 
| T99 | 
67142 | 
582 | 
0 | 
0 | 
| T101 | 
108165 | 
903 | 
0 | 
0 | 
| T115 | 
14426 | 
84 | 
0 | 
0 | 
| T117 | 
15404 | 
107 | 
0 | 
0 | 
| T120 | 
9219 | 
63 | 
0 | 
0 | 
| T124 | 
10057 | 
51 | 
0 | 
0 | 
| T128 | 
10742 | 
129 | 
0 | 
0 | 
| T129 | 
78860 | 
120 | 
0 | 
0 | 
| T155 | 
41578 | 
258 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
5998 | 
0 | 
0 | 
| T80 | 
3352 | 
5 | 
0 | 
0 | 
| T99 | 
67142 | 
463 | 
0 | 
0 | 
| T101 | 
108165 | 
719 | 
0 | 
0 | 
| T115 | 
14426 | 
69 | 
0 | 
0 | 
| T117 | 
15404 | 
165 | 
0 | 
0 | 
| T120 | 
9219 | 
145 | 
0 | 
0 | 
| T124 | 
10057 | 
8 | 
0 | 
0 | 
| T128 | 
10742 | 
126 | 
0 | 
0 | 
| T129 | 
78860 | 
133 | 
0 | 
0 | 
| T155 | 
41578 | 
246 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6151 | 
0 | 
0 | 
| T80 | 
3352 | 
13 | 
0 | 
0 | 
| T99 | 
67142 | 
488 | 
0 | 
0 | 
| T101 | 
108165 | 
827 | 
0 | 
0 | 
| T115 | 
14426 | 
116 | 
0 | 
0 | 
| T117 | 
15404 | 
110 | 
0 | 
0 | 
| T120 | 
9219 | 
55 | 
0 | 
0 | 
| T124 | 
10057 | 
93 | 
0 | 
0 | 
| T128 | 
10742 | 
68 | 
0 | 
0 | 
| T129 | 
78860 | 
110 | 
0 | 
0 | 
| T155 | 
41578 | 
280 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6037 | 
0 | 
0 | 
| T80 | 
3352 | 
2 | 
0 | 
0 | 
| T99 | 
67142 | 
392 | 
0 | 
0 | 
| T101 | 
108165 | 
554 | 
0 | 
0 | 
| T115 | 
14426 | 
70 | 
0 | 
0 | 
| T117 | 
15404 | 
27 | 
0 | 
0 | 
| T120 | 
9219 | 
153 | 
0 | 
0 | 
| T124 | 
10057 | 
105 | 
0 | 
0 | 
| T128 | 
10742 | 
66 | 
0 | 
0 | 
| T129 | 
78860 | 
104 | 
0 | 
0 | 
| T155 | 
41578 | 
256 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6064 | 
0 | 
0 | 
| T80 | 
3352 | 
12 | 
0 | 
0 | 
| T99 | 
67142 | 
549 | 
0 | 
0 | 
| T101 | 
108165 | 
982 | 
0 | 
0 | 
| T115 | 
14426 | 
56 | 
0 | 
0 | 
| T117 | 
15404 | 
71 | 
0 | 
0 | 
| T120 | 
9219 | 
54 | 
0 | 
0 | 
| T124 | 
10057 | 
58 | 
0 | 
0 | 
| T128 | 
10742 | 
107 | 
0 | 
0 | 
| T129 | 
78860 | 
127 | 
0 | 
0 | 
| T155 | 
41578 | 
283 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6268 | 
0 | 
0 | 
| T80 | 
3352 | 
9 | 
0 | 
0 | 
| T99 | 
67142 | 
457 | 
0 | 
0 | 
| T101 | 
108165 | 
791 | 
0 | 
0 | 
| T111 | 
23305 | 
8 | 
0 | 
0 | 
| T115 | 
14426 | 
74 | 
0 | 
0 | 
| T117 | 
15404 | 
146 | 
0 | 
0 | 
| T120 | 
9219 | 
50 | 
0 | 
0 | 
| T124 | 
10057 | 
59 | 
0 | 
0 | 
| T128 | 
10742 | 
61 | 
0 | 
0 | 
| T129 | 
78860 | 
136 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6326 | 
0 | 
0 | 
| T80 | 
3352 | 
11 | 
0 | 
0 | 
| T99 | 
67142 | 
674 | 
0 | 
0 | 
| T101 | 
108165 | 
872 | 
0 | 
0 | 
| T115 | 
14426 | 
72 | 
0 | 
0 | 
| T117 | 
15404 | 
105 | 
0 | 
0 | 
| T120 | 
9219 | 
112 | 
0 | 
0 | 
| T124 | 
10057 | 
68 | 
0 | 
0 | 
| T128 | 
10742 | 
104 | 
0 | 
0 | 
| T129 | 
78860 | 
115 | 
0 | 
0 | 
| T155 | 
41578 | 
212 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6282 | 
0 | 
0 | 
| T80 | 
3352 | 
13 | 
0 | 
0 | 
| T99 | 
67142 | 
584 | 
0 | 
0 | 
| T101 | 
108165 | 
823 | 
0 | 
0 | 
| T115 | 
14426 | 
94 | 
0 | 
0 | 
| T117 | 
15404 | 
113 | 
0 | 
0 | 
| T120 | 
9219 | 
51 | 
0 | 
0 | 
| T124 | 
10057 | 
137 | 
0 | 
0 | 
| T128 | 
10742 | 
98 | 
0 | 
0 | 
| T129 | 
78860 | 
126 | 
0 | 
0 | 
| T155 | 
41578 | 
254 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6282 | 
0 | 
0 | 
| T80 | 
3352 | 
12 | 
0 | 
0 | 
| T99 | 
67142 | 
533 | 
0 | 
0 | 
| T101 | 
108165 | 
935 | 
0 | 
0 | 
| T115 | 
14426 | 
22 | 
0 | 
0 | 
| T117 | 
15404 | 
108 | 
0 | 
0 | 
| T120 | 
9219 | 
69 | 
0 | 
0 | 
| T124 | 
10057 | 
8 | 
0 | 
0 | 
| T128 | 
10742 | 
169 | 
0 | 
0 | 
| T129 | 
78860 | 
148 | 
0 | 
0 | 
| T155 | 
41578 | 
245 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6700 | 
0 | 
0 | 
| T80 | 
3352 | 
9 | 
0 | 
0 | 
| T99 | 
67142 | 
664 | 
0 | 
0 | 
| T101 | 
108165 | 
1019 | 
0 | 
0 | 
| T115 | 
14426 | 
60 | 
0 | 
0 | 
| T117 | 
15404 | 
68 | 
0 | 
0 | 
| T120 | 
9219 | 
49 | 
0 | 
0 | 
| T124 | 
10057 | 
96 | 
0 | 
0 | 
| T128 | 
10742 | 
87 | 
0 | 
0 | 
| T129 | 
78860 | 
145 | 
0 | 
0 | 
| T155 | 
41578 | 
254 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6397 | 
0 | 
0 | 
| T80 | 
3352 | 
10 | 
0 | 
0 | 
| T99 | 
67142 | 
437 | 
0 | 
0 | 
| T101 | 
108165 | 
777 | 
0 | 
0 | 
| T115 | 
14426 | 
59 | 
0 | 
0 | 
| T117 | 
15404 | 
151 | 
0 | 
0 | 
| T120 | 
9219 | 
5 | 
0 | 
0 | 
| T124 | 
10057 | 
123 | 
0 | 
0 | 
| T128 | 
10742 | 
87 | 
0 | 
0 | 
| T129 | 
78860 | 
140 | 
0 | 
0 | 
| T155 | 
41578 | 
276 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6583 | 
0 | 
0 | 
| T80 | 
3352 | 
8 | 
0 | 
0 | 
| T99 | 
67142 | 
532 | 
0 | 
0 | 
| T101 | 
108165 | 
1025 | 
0 | 
0 | 
| T115 | 
14426 | 
66 | 
0 | 
0 | 
| T117 | 
15404 | 
131 | 
0 | 
0 | 
| T120 | 
9219 | 
62 | 
0 | 
0 | 
| T124 | 
10057 | 
169 | 
0 | 
0 | 
| T128 | 
10742 | 
96 | 
0 | 
0 | 
| T129 | 
78860 | 
82 | 
0 | 
0 | 
| T155 | 
41578 | 
277 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6103 | 
0 | 
0 | 
| T80 | 
3352 | 
1 | 
0 | 
0 | 
| T99 | 
67142 | 
524 | 
0 | 
0 | 
| T101 | 
108165 | 
886 | 
0 | 
0 | 
| T115 | 
14426 | 
130 | 
0 | 
0 | 
| T117 | 
15404 | 
53 | 
0 | 
0 | 
| T120 | 
9219 | 
66 | 
0 | 
0 | 
| T124 | 
10057 | 
97 | 
0 | 
0 | 
| T128 | 
10742 | 
87 | 
0 | 
0 | 
| T129 | 
78860 | 
131 | 
0 | 
0 | 
| T155 | 
41578 | 
306 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6214 | 
0 | 
0 | 
| T80 | 
3352 | 
9 | 
0 | 
0 | 
| T99 | 
67142 | 
583 | 
0 | 
0 | 
| T101 | 
108165 | 
791 | 
0 | 
0 | 
| T115 | 
14426 | 
115 | 
0 | 
0 | 
| T117 | 
15404 | 
86 | 
0 | 
0 | 
| T120 | 
9219 | 
14 | 
0 | 
0 | 
| T124 | 
10057 | 
23 | 
0 | 
0 | 
| T128 | 
10742 | 
122 | 
0 | 
0 | 
| T129 | 
78860 | 
120 | 
0 | 
0 | 
| T155 | 
41578 | 
269 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6572 | 
0 | 
0 | 
| T80 | 
3352 | 
7 | 
0 | 
0 | 
| T99 | 
67142 | 
781 | 
0 | 
0 | 
| T101 | 
108165 | 
1058 | 
0 | 
0 | 
| T115 | 
14426 | 
120 | 
0 | 
0 | 
| T117 | 
15404 | 
157 | 
0 | 
0 | 
| T120 | 
9219 | 
37 | 
0 | 
0 | 
| T124 | 
10057 | 
72 | 
0 | 
0 | 
| T128 | 
10742 | 
45 | 
0 | 
0 | 
| T129 | 
78860 | 
109 | 
0 | 
0 | 
| T155 | 
41578 | 
278 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6208 | 
0 | 
0 | 
| T80 | 
3352 | 
8 | 
0 | 
0 | 
| T99 | 
67142 | 
478 | 
0 | 
0 | 
| T101 | 
108165 | 
670 | 
0 | 
0 | 
| T115 | 
14426 | 
39 | 
0 | 
0 | 
| T117 | 
15404 | 
170 | 
0 | 
0 | 
| T120 | 
9219 | 
62 | 
0 | 
0 | 
| T124 | 
10057 | 
101 | 
0 | 
0 | 
| T128 | 
10742 | 
143 | 
0 | 
0 | 
| T129 | 
78860 | 
129 | 
0 | 
0 | 
| T155 | 
41578 | 
260 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
5817 | 
0 | 
0 | 
| T80 | 
3352 | 
10 | 
0 | 
0 | 
| T99 | 
67142 | 
420 | 
0 | 
0 | 
| T101 | 
108165 | 
787 | 
0 | 
0 | 
| T115 | 
14426 | 
56 | 
0 | 
0 | 
| T117 | 
15404 | 
114 | 
0 | 
0 | 
| T120 | 
9219 | 
68 | 
0 | 
0 | 
| T124 | 
10057 | 
77 | 
0 | 
0 | 
| T128 | 
10742 | 
60 | 
0 | 
0 | 
| T129 | 
78860 | 
183 | 
0 | 
0 | 
| T155 | 
41578 | 
291 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6536 | 
0 | 
0 | 
| T80 | 
3352 | 
7 | 
0 | 
0 | 
| T99 | 
67142 | 
688 | 
0 | 
0 | 
| T101 | 
108165 | 
807 | 
0 | 
0 | 
| T115 | 
14426 | 
60 | 
0 | 
0 | 
| T117 | 
15404 | 
129 | 
0 | 
0 | 
| T120 | 
9219 | 
80 | 
0 | 
0 | 
| T124 | 
10057 | 
126 | 
0 | 
0 | 
| T128 | 
10742 | 
55 | 
0 | 
0 | 
| T129 | 
78860 | 
112 | 
0 | 
0 | 
| T155 | 
41578 | 
247 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
5907 | 
0 | 
0 | 
| T80 | 
3352 | 
7 | 
0 | 
0 | 
| T99 | 
67142 | 
504 | 
0 | 
0 | 
| T101 | 
108165 | 
669 | 
0 | 
0 | 
| T115 | 
14426 | 
66 | 
0 | 
0 | 
| T117 | 
15404 | 
120 | 
0 | 
0 | 
| T120 | 
9219 | 
82 | 
0 | 
0 | 
| T124 | 
10057 | 
128 | 
0 | 
0 | 
| T128 | 
10742 | 
102 | 
0 | 
0 | 
| T129 | 
78860 | 
182 | 
0 | 
0 | 
| T155 | 
41578 | 
264 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
5789 | 
0 | 
0 | 
| T80 | 
3352 | 
7 | 
0 | 
0 | 
| T99 | 
67142 | 
603 | 
0 | 
0 | 
| T101 | 
108165 | 
486 | 
0 | 
0 | 
| T115 | 
14426 | 
42 | 
0 | 
0 | 
| T117 | 
15404 | 
118 | 
0 | 
0 | 
| T120 | 
9219 | 
76 | 
0 | 
0 | 
| T124 | 
10057 | 
9 | 
0 | 
0 | 
| T128 | 
10742 | 
12 | 
0 | 
0 | 
| T129 | 
78860 | 
143 | 
0 | 
0 | 
| T155 | 
41578 | 
241 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
5772 | 
0 | 
0 | 
| T80 | 
3352 | 
13 | 
0 | 
0 | 
| T99 | 
67142 | 
688 | 
0 | 
0 | 
| T101 | 
108165 | 
642 | 
0 | 
0 | 
| T111 | 
23305 | 
6 | 
0 | 
0 | 
| T115 | 
14426 | 
80 | 
0 | 
0 | 
| T117 | 
15404 | 
80 | 
0 | 
0 | 
| T120 | 
9219 | 
51 | 
0 | 
0 | 
| T124 | 
10057 | 
47 | 
0 | 
0 | 
| T128 | 
10742 | 
90 | 
0 | 
0 | 
| T129 | 
78860 | 
127 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6212 | 
0 | 
0 | 
| T80 | 
3352 | 
2 | 
0 | 
0 | 
| T99 | 
67142 | 
748 | 
0 | 
0 | 
| T101 | 
108165 | 
778 | 
0 | 
0 | 
| T115 | 
14426 | 
33 | 
0 | 
0 | 
| T117 | 
15404 | 
24 | 
0 | 
0 | 
| T120 | 
9219 | 
153 | 
0 | 
0 | 
| T124 | 
10057 | 
66 | 
0 | 
0 | 
| T128 | 
10742 | 
159 | 
0 | 
0 | 
| T129 | 
78860 | 
145 | 
0 | 
0 | 
| T155 | 
41578 | 
280 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6182 | 
0 | 
0 | 
| T80 | 
3352 | 
10 | 
0 | 
0 | 
| T99 | 
67142 | 
547 | 
0 | 
0 | 
| T101 | 
108165 | 
1100 | 
0 | 
0 | 
| T115 | 
14426 | 
130 | 
0 | 
0 | 
| T117 | 
15404 | 
23 | 
0 | 
0 | 
| T120 | 
9219 | 
13 | 
0 | 
0 | 
| T124 | 
10057 | 
86 | 
0 | 
0 | 
| T128 | 
10742 | 
15 | 
0 | 
0 | 
| T129 | 
78860 | 
101 | 
0 | 
0 | 
| T155 | 
41578 | 
260 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
6065 | 
0 | 
0 | 
| T80 | 
3352 | 
2 | 
0 | 
0 | 
| T99 | 
67142 | 
488 | 
0 | 
0 | 
| T101 | 
108165 | 
851 | 
0 | 
0 | 
| T115 | 
14426 | 
71 | 
0 | 
0 | 
| T117 | 
15404 | 
127 | 
0 | 
0 | 
| T120 | 
9219 | 
37 | 
0 | 
0 | 
| T124 | 
10057 | 
63 | 
0 | 
0 | 
| T128 | 
10742 | 
47 | 
0 | 
0 | 
| T129 | 
78860 | 
168 | 
0 | 
0 | 
| T155 | 
41578 | 
247 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2868 | 
0 | 
0 | 
| T80 | 
3352 | 
1 | 
0 | 
0 | 
| T99 | 
67142 | 
95 | 
0 | 
0 | 
| T101 | 
108165 | 
146 | 
0 | 
0 | 
| T115 | 
14426 | 
22 | 
0 | 
0 | 
| T117 | 
15404 | 
37 | 
0 | 
0 | 
| T120 | 
9219 | 
20 | 
0 | 
0 | 
| T124 | 
10057 | 
28 | 
0 | 
0 | 
| T128 | 
10742 | 
18 | 
0 | 
0 | 
| T129 | 
78860 | 
121 | 
0 | 
0 | 
| T155 | 
41578 | 
254 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2980 | 
0 | 
0 | 
| T80 | 
3352 | 
2 | 
0 | 
0 | 
| T99 | 
67142 | 
107 | 
0 | 
0 | 
| T101 | 
108165 | 
153 | 
0 | 
0 | 
| T115 | 
14426 | 
31 | 
0 | 
0 | 
| T117 | 
15404 | 
25 | 
0 | 
0 | 
| T120 | 
9219 | 
20 | 
0 | 
0 | 
| T124 | 
10057 | 
17 | 
0 | 
0 | 
| T128 | 
10742 | 
16 | 
0 | 
0 | 
| T129 | 
78860 | 
128 | 
0 | 
0 | 
| T155 | 
41578 | 
268 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2954 | 
0 | 
0 | 
| T80 | 
3352 | 
10 | 
0 | 
0 | 
| T99 | 
67142 | 
150 | 
0 | 
0 | 
| T101 | 
108165 | 
165 | 
0 | 
0 | 
| T115 | 
14426 | 
29 | 
0 | 
0 | 
| T117 | 
15404 | 
36 | 
0 | 
0 | 
| T120 | 
9219 | 
8 | 
0 | 
0 | 
| T124 | 
10057 | 
18 | 
0 | 
0 | 
| T128 | 
10742 | 
18 | 
0 | 
0 | 
| T129 | 
78860 | 
157 | 
0 | 
0 | 
| T155 | 
41578 | 
282 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2989 | 
0 | 
0 | 
| T80 | 
3352 | 
6 | 
0 | 
0 | 
| T99 | 
67142 | 
131 | 
0 | 
0 | 
| T101 | 
108165 | 
164 | 
0 | 
0 | 
| T115 | 
14426 | 
21 | 
0 | 
0 | 
| T117 | 
15404 | 
28 | 
0 | 
0 | 
| T120 | 
9219 | 
10 | 
0 | 
0 | 
| T124 | 
10057 | 
13 | 
0 | 
0 | 
| T128 | 
10742 | 
12 | 
0 | 
0 | 
| T129 | 
78860 | 
179 | 
0 | 
0 | 
| T155 | 
41578 | 
284 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
3558 | 
0 | 
0 | 
| T80 | 
3352 | 
5 | 
0 | 
0 | 
| T99 | 
67142 | 
223 | 
0 | 
0 | 
| T101 | 
108165 | 
226 | 
0 | 
0 | 
| T115 | 
14426 | 
24 | 
0 | 
0 | 
| T117 | 
15404 | 
54 | 
0 | 
0 | 
| T120 | 
9219 | 
23 | 
0 | 
0 | 
| T124 | 
10057 | 
34 | 
0 | 
0 | 
| T128 | 
10742 | 
22 | 
0 | 
0 | 
| T129 | 
78860 | 
158 | 
0 | 
0 | 
| T155 | 
41578 | 
257 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
5252 | 
0 | 
0 | 
| T20 | 
158182 | 
56 | 
0 | 
0 | 
| T22 | 
0 | 
19 | 
0 | 
0 | 
| T32 | 
0 | 
16 | 
0 | 
0 | 
| T49 | 
0 | 
15 | 
0 | 
0 | 
| T52 | 
15813 | 
0 | 
0 | 
0 | 
| T53 | 
7172 | 
0 | 
0 | 
0 | 
| T54 | 
14693 | 
0 | 
0 | 
0 | 
| T55 | 
1523 | 
0 | 
0 | 
0 | 
| T56 | 
33537 | 
0 | 
0 | 
0 | 
| T57 | 
5087 | 
0 | 
0 | 
0 | 
| T58 | 
216331 | 
0 | 
0 | 
0 | 
| T62 | 
1322 | 
0 | 
0 | 
0 | 
| T157 | 
0 | 
33 | 
0 | 
0 | 
| T158 | 
0 | 
24 | 
0 | 
0 | 
| T159 | 
0 | 
17 | 
0 | 
0 | 
| T160 | 
0 | 
28 | 
0 | 
0 | 
| T161 | 
0 | 
68 | 
0 | 
0 | 
| T162 | 
0 | 
37 | 
0 | 
0 | 
| T163 | 
1474 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2919 | 
0 | 
0 | 
| T80 | 
3352 | 
2 | 
0 | 
0 | 
| T99 | 
67142 | 
134 | 
0 | 
0 | 
| T101 | 
108165 | 
163 | 
0 | 
0 | 
| T115 | 
14426 | 
29 | 
0 | 
0 | 
| T117 | 
15404 | 
14 | 
0 | 
0 | 
| T120 | 
9219 | 
14 | 
0 | 
0 | 
| T124 | 
10057 | 
30 | 
0 | 
0 | 
| T128 | 
10742 | 
19 | 
0 | 
0 | 
| T129 | 
78860 | 
126 | 
0 | 
0 | 
| T155 | 
41578 | 
234 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2991 | 
0 | 
0 | 
| T80 | 
3352 | 
9 | 
0 | 
0 | 
| T99 | 
67142 | 
102 | 
0 | 
0 | 
| T101 | 
108165 | 
181 | 
0 | 
0 | 
| T115 | 
14426 | 
18 | 
0 | 
0 | 
| T117 | 
15404 | 
44 | 
0 | 
0 | 
| T120 | 
9219 | 
16 | 
0 | 
0 | 
| T124 | 
10057 | 
20 | 
0 | 
0 | 
| T128 | 
10742 | 
9 | 
0 | 
0 | 
| T129 | 
78860 | 
113 | 
0 | 
0 | 
| T155 | 
41578 | 
274 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2610 | 
0 | 
0 | 
| T80 | 
3352 | 
11 | 
0 | 
0 | 
| T99 | 
67142 | 
73 | 
0 | 
0 | 
| T101 | 
108165 | 
126 | 
0 | 
0 | 
| T115 | 
14426 | 
31 | 
0 | 
0 | 
| T117 | 
15404 | 
21 | 
0 | 
0 | 
| T120 | 
9219 | 
5 | 
0 | 
0 | 
| T124 | 
10057 | 
4 | 
0 | 
0 | 
| T128 | 
10742 | 
5 | 
0 | 
0 | 
| T129 | 
78860 | 
157 | 
0 | 
0 | 
| T155 | 
41578 | 
243 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2618 | 
0 | 
0 | 
| T80 | 
3352 | 
17 | 
0 | 
0 | 
| T99 | 
67142 | 
70 | 
0 | 
0 | 
| T101 | 
108165 | 
122 | 
0 | 
0 | 
| T115 | 
14426 | 
22 | 
0 | 
0 | 
| T117 | 
15404 | 
22 | 
0 | 
0 | 
| T120 | 
9219 | 
9 | 
0 | 
0 | 
| T124 | 
10057 | 
14 | 
0 | 
0 | 
| T128 | 
10742 | 
14 | 
0 | 
0 | 
| T129 | 
78860 | 
153 | 
0 | 
0 | 
| T155 | 
41578 | 
252 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2629 | 
0 | 
0 | 
| T80 | 
3352 | 
2 | 
0 | 
0 | 
| T99 | 
67142 | 
73 | 
0 | 
0 | 
| T101 | 
108165 | 
79 | 
0 | 
0 | 
| T115 | 
14426 | 
12 | 
0 | 
0 | 
| T117 | 
15404 | 
31 | 
0 | 
0 | 
| T120 | 
9219 | 
16 | 
0 | 
0 | 
| T124 | 
10057 | 
16 | 
0 | 
0 | 
| T128 | 
10742 | 
8 | 
0 | 
0 | 
| T129 | 
78860 | 
143 | 
0 | 
0 | 
| T155 | 
41578 | 
241 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2760 | 
0 | 
0 | 
| T80 | 
3352 | 
12 | 
0 | 
0 | 
| T99 | 
67142 | 
71 | 
0 | 
0 | 
| T101 | 
108165 | 
117 | 
0 | 
0 | 
| T115 | 
14426 | 
25 | 
0 | 
0 | 
| T117 | 
15404 | 
26 | 
0 | 
0 | 
| T120 | 
9219 | 
8 | 
0 | 
0 | 
| T124 | 
10057 | 
11 | 
0 | 
0 | 
| T128 | 
10742 | 
13 | 
0 | 
0 | 
| T129 | 
78860 | 
150 | 
0 | 
0 | 
| T155 | 
41578 | 
267 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
3605 | 
0 | 
0 | 
| T80 | 
3352 | 
4 | 
0 | 
0 | 
| T99 | 
67142 | 
212 | 
0 | 
0 | 
| T101 | 
108165 | 
218 | 
0 | 
0 | 
| T115 | 
14426 | 
33 | 
0 | 
0 | 
| T117 | 
15404 | 
57 | 
0 | 
0 | 
| T120 | 
9219 | 
33 | 
0 | 
0 | 
| T124 | 
10057 | 
8 | 
0 | 
0 | 
| T128 | 
10742 | 
32 | 
0 | 
0 | 
| T129 | 
78860 | 
122 | 
0 | 
0 | 
| T155 | 
41578 | 
256 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2689 | 
0 | 
0 | 
| T80 | 
3352 | 
6 | 
0 | 
0 | 
| T99 | 
67142 | 
87 | 
0 | 
0 | 
| T101 | 
108165 | 
93 | 
0 | 
0 | 
| T115 | 
14426 | 
31 | 
0 | 
0 | 
| T117 | 
15404 | 
21 | 
0 | 
0 | 
| T120 | 
9219 | 
8 | 
0 | 
0 | 
| T124 | 
10057 | 
17 | 
0 | 
0 | 
| T128 | 
10742 | 
6 | 
0 | 
0 | 
| T129 | 
78860 | 
152 | 
0 | 
0 | 
| T155 | 
41578 | 
254 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
3493 | 
0 | 
0 | 
| T80 | 
3352 | 
10 | 
0 | 
0 | 
| T99 | 
67142 | 
133 | 
0 | 
0 | 
| T101 | 
108165 | 
298 | 
0 | 
0 | 
| T115 | 
14426 | 
53 | 
0 | 
0 | 
| T117 | 
15404 | 
71 | 
0 | 
0 | 
| T120 | 
9219 | 
48 | 
0 | 
0 | 
| T124 | 
10057 | 
18 | 
0 | 
0 | 
| T128 | 
10742 | 
10 | 
0 | 
0 | 
| T129 | 
78860 | 
169 | 
0 | 
0 | 
| T155 | 
41578 | 
247 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2912 | 
0 | 
0 | 
| T80 | 
3352 | 
4 | 
0 | 
0 | 
| T99 | 
67142 | 
127 | 
0 | 
0 | 
| T101 | 
108165 | 
179 | 
0 | 
0 | 
| T115 | 
14426 | 
37 | 
0 | 
0 | 
| T117 | 
15404 | 
17 | 
0 | 
0 | 
| T120 | 
9219 | 
30 | 
0 | 
0 | 
| T124 | 
10057 | 
10 | 
0 | 
0 | 
| T128 | 
10742 | 
13 | 
0 | 
0 | 
| T129 | 
78860 | 
109 | 
0 | 
0 | 
| T155 | 
41578 | 
250 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2714 | 
0 | 
0 | 
| T80 | 
3352 | 
1 | 
0 | 
0 | 
| T99 | 
67142 | 
82 | 
0 | 
0 | 
| T101 | 
108165 | 
121 | 
0 | 
0 | 
| T115 | 
14426 | 
25 | 
0 | 
0 | 
| T117 | 
15404 | 
24 | 
0 | 
0 | 
| T120 | 
9219 | 
14 | 
0 | 
0 | 
| T124 | 
10057 | 
7 | 
0 | 
0 | 
| T128 | 
10742 | 
12 | 
0 | 
0 | 
| T129 | 
78860 | 
159 | 
0 | 
0 | 
| T155 | 
41578 | 
214 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2589 | 
0 | 
0 | 
| T80 | 
3352 | 
5 | 
0 | 
0 | 
| T99 | 
67142 | 
65 | 
0 | 
0 | 
| T101 | 
108165 | 
141 | 
0 | 
0 | 
| T115 | 
14426 | 
23 | 
0 | 
0 | 
| T117 | 
15404 | 
35 | 
0 | 
0 | 
| T120 | 
9219 | 
8 | 
0 | 
0 | 
| T124 | 
10057 | 
10 | 
0 | 
0 | 
| T128 | 
10742 | 
7 | 
0 | 
0 | 
| T129 | 
78860 | 
150 | 
0 | 
0 | 
| T155 | 
41578 | 
223 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2723 | 
0 | 
0 | 
| T80 | 
3352 | 
13 | 
0 | 
0 | 
| T99 | 
67142 | 
64 | 
0 | 
0 | 
| T101 | 
108165 | 
100 | 
0 | 
0 | 
| T115 | 
14426 | 
30 | 
0 | 
0 | 
| T117 | 
15404 | 
39 | 
0 | 
0 | 
| T120 | 
9219 | 
5 | 
0 | 
0 | 
| T124 | 
10057 | 
6 | 
0 | 
0 | 
| T128 | 
10742 | 
11 | 
0 | 
0 | 
| T129 | 
78860 | 
117 | 
0 | 
0 | 
| T155 | 
41578 | 
268 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2642 | 
0 | 
0 | 
| T80 | 
3352 | 
6 | 
0 | 
0 | 
| T99 | 
67142 | 
87 | 
0 | 
0 | 
| T101 | 
108165 | 
153 | 
0 | 
0 | 
| T115 | 
14426 | 
25 | 
0 | 
0 | 
| T117 | 
15404 | 
22 | 
0 | 
0 | 
| T120 | 
9219 | 
6 | 
0 | 
0 | 
| T124 | 
10057 | 
2 | 
0 | 
0 | 
| T128 | 
10742 | 
18 | 
0 | 
0 | 
| T129 | 
78860 | 
106 | 
0 | 
0 | 
| T155 | 
41578 | 
249 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2741 | 
0 | 
0 | 
| T80 | 
3352 | 
3 | 
0 | 
0 | 
| T99 | 
67142 | 
79 | 
0 | 
0 | 
| T101 | 
108165 | 
149 | 
0 | 
0 | 
| T115 | 
14426 | 
22 | 
0 | 
0 | 
| T117 | 
15404 | 
15 | 
0 | 
0 | 
| T120 | 
9219 | 
5 | 
0 | 
0 | 
| T124 | 
10057 | 
9 | 
0 | 
0 | 
| T128 | 
10742 | 
12 | 
0 | 
0 | 
| T129 | 
78860 | 
164 | 
0 | 
0 | 
| T155 | 
41578 | 
273 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
473708879 | 
2899 | 
0 | 
0 | 
| T80 | 
3352 | 
4 | 
0 | 
0 | 
| T99 | 
67142 | 
67 | 
0 | 
0 | 
| T101 | 
108165 | 
132 | 
0 | 
0 | 
| T115 | 
14426 | 
16 | 
0 | 
0 | 
| T117 | 
15404 | 
25 | 
0 | 
0 | 
| T120 | 
9219 | 
10 | 
0 | 
0 | 
| T124 | 
10057 | 
8 | 
0 | 
0 | 
| T128 | 
10742 | 
7 | 
0 | 
0 | 
| T129 | 
78860 | 
154 | 
0 | 
0 | 
| T155 | 
41578 | 
261 | 
0 | 
0 |