Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3575576	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4201264

1

T2

1

T4

105

T5

99

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4358943	1			T1	1		T2	71		T3	1
values[0x0]	1708502	1			T4	50		T5	44		T6	1
values[0x1]	1709395	1			T3	1		T4	50		T5	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2542081	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5234759

1

T2

21

T3

1

T4

159

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26937	1			T7	2		T11	6		T14	1
valid_sources[0x01]	29841	1			T7	2		T8	1		T27	2
valid_sources[0x02]	26756	1			T7	4		T10	2		T27	1
valid_sources[0x03]	29306	1			T7	5		T10	8		T11	5
valid_sources[0x04]	29241	1			T2	3		T7	2		T10	2
valid_sources[0x05]	57567	1			T7	3		T10	3		T11	6
valid_sources[0x06]	32269	1			T7	4		T11	6		T14	2
valid_sources[0x07]	31337	1			T7	2		T11	7		T14	2
valid_sources[0x08]	31041	1			T7	3		T10	2		T11	4
valid_sources[0x09]	45376	1			T7	5		T27	4		T11	11
valid_sources[0x0a]	29758	1			T7	6		T8	1		T10	5
valid_sources[0x0b]	32735	1			T7	2		T8	1		T10	10
valid_sources[0x0c]	29875	1			T2	2		T7	8		T8	1
valid_sources[0x0d]	30354	1			T10	9		T27	1		T11	8
valid_sources[0x0e]	29090	1			T1	1		T7	4		T10	3
valid_sources[0x0f]	28686	1			T7	4		T8	1		T10	1
valid_sources[0x10]	27457	1			T2	1		T7	3		T10	7
valid_sources[0x11]	27567	1			T2	1		T7	4		T10	8
valid_sources[0x12]	32558	1			T7	2		T11	6		T15	9
valid_sources[0x13]	28065	1			T7	3		T8	1		T27	2
valid_sources[0x14]	27302	1			T2	1		T10	4		T27	1
valid_sources[0x15]	31258	1			T7	4		T11	4		T14	2
valid_sources[0x16]	28272	1			T7	3		T10	1		T11	7
valid_sources[0x17]	30334	1			T7	3		T11	2		T14	1
valid_sources[0x18]	31945	1			T7	5		T10	3		T27	2
valid_sources[0x19]	33657	1			T7	6		T10	8		T27	1
valid_sources[0x1a]	30543	1			T7	4		T10	6		T11	7
valid_sources[0x1b]	29566	1			T2	1		T7	5		T10	12
valid_sources[0x1c]	26939	1			T7	3		T27	4		T11	1
valid_sources[0x1d]	27346	1			T7	4		T10	7		T27	1
valid_sources[0x1e]	28756	1			T2	2		T7	3		T10	6
valid_sources[0x1f]	28580	1			T2	1		T7	1		T10	2
valid_sources[0x20]	28720	1			T7	2		T27	1		T11	6
valid_sources[0x21]	27892	1			T7	5		T10	1		T27	2
valid_sources[0x22]	29821	1			T2	1		T7	1		T10	10
valid_sources[0x23]	28329	1			T7	1		T10	4		T11	8
valid_sources[0x24]	29102	1			T2	1		T7	4		T10	10
valid_sources[0x25]	29973	1			T8	1		T10	2		T11	4
valid_sources[0x26]	27813	1			T7	6		T10	2		T27	1
valid_sources[0x27]	29646	1			T7	3		T8	1		T10	16
valid_sources[0x28]	27614	1			T7	5		T8	1		T10	5
valid_sources[0x29]	31132	1			T7	3		T27	1		T11	5
valid_sources[0x2a]	34175	1			T2	1		T7	1		T27	1
valid_sources[0x2b]	28310	1			T7	5		T10	7		T11	4
valid_sources[0x2c]	29846	1			T7	4		T10	6		T11	8
valid_sources[0x2d]	28592	1			T7	3		T8	1		T10	3
valid_sources[0x2e]	27432	1			T7	5		T8	2		T10	4
valid_sources[0x2f]	31131	1			T7	1		T10	2		T11	8
valid_sources[0x30]	28737	1			T7	6		T8	1		T10	3
valid_sources[0x31]	28262	1			T2	2		T7	4		T11	9
valid_sources[0x32]	31357	1			T7	4		T10	15		T27	3
valid_sources[0x33]	27572	1			T7	3		T10	1		T11	2
valid_sources[0x34]	27020	1			T7	4		T11	5		T14	4
valid_sources[0x35]	27733	1			T7	3		T10	1		T27	3
valid_sources[0x36]	28186	1			T7	3		T11	6		T14	3
valid_sources[0x37]	29309	1			T7	6		T10	8		T11	6
valid_sources[0x38]	31507	1			T27	2		T11	4		T14	7
valid_sources[0x39]	37685	1			T7	3		T10	5		T27	1
valid_sources[0x3a]	30315	1			T7	3		T8	1		T10	2
valid_sources[0x3b]	30606	1			T7	7		T8	1		T27	4
valid_sources[0x3c]	27738	1			T7	1		T10	2		T11	7
valid_sources[0x3d]	29279	1			T2	1		T7	2		T10	3
valid_sources[0x3e]	26601	1			T10	4		T11	8		T14	5
valid_sources[0x3f]	38426	1			T7	1		T10	2		T11	8
valid_sources[0x40]	29076	1			T7	5		T10	6		T27	2
valid_sources[0x41]	27277	1			T7	2		T10	3		T11	7
valid_sources[0x42]	31713	1			T7	3		T10	5		T27	3
valid_sources[0x43]	30831	1			T2	2		T7	4		T11	5
valid_sources[0x44]	30971	1			T7	4		T8	1		T10	8
valid_sources[0x45]	29739	1			T7	5		T11	3		T14	4
valid_sources[0x46]	29050	1			T2	1		T7	3		T10	2
valid_sources[0x47]	30027	1			T7	3		T27	5		T11	6
valid_sources[0x48]	29435	1			T7	3		T10	10		T27	3
valid_sources[0x49]	29840	1			T7	3		T8	1		T10	2
valid_sources[0x4a]	29836	1			T7	4		T10	12		T27	1
valid_sources[0x4b]	30913	1			T7	1		T11	4		T14	10
valid_sources[0x4c]	29997	1			T7	3		T10	2		T11	7
valid_sources[0x4d]	26425	1			T2	1		T7	3		T10	2
valid_sources[0x4e]	27774	1			T7	5		T10	25		T11	5
valid_sources[0x4f]	30380	1			T7	4		T8	2		T10	6
valid_sources[0x50]	32420	1			T7	4		T11	5		T14	5
valid_sources[0x51]	35692	1			T7	1		T27	1		T11	4
valid_sources[0x52]	28942	1			T7	4		T27	2		T11	7
valid_sources[0x53]	26437	1			T7	2		T10	8		T27	1
valid_sources[0x54]	29673	1			T7	6		T8	1		T10	6
valid_sources[0x55]	31293	1			T7	2		T27	2		T11	7
valid_sources[0x56]	30042	1			T7	3		T8	1		T11	16
valid_sources[0x57]	26746	1			T7	5		T10	11		T27	1
valid_sources[0x58]	25755	1			T7	1		T10	11		T27	1
valid_sources[0x59]	30623	1			T7	3		T11	8		T14	6
valid_sources[0x5a]	30055	1			T7	2		T10	2		T11	10
valid_sources[0x5b]	35177	1			T7	3		T10	1		T11	6
valid_sources[0x5c]	32395	1			T10	4		T27	2		T11	5
valid_sources[0x5d]	29886	1			T2	1		T7	3		T10	1
valid_sources[0x5e]	31339	1			T7	4		T11	3		T14	2
valid_sources[0x5f]	27278	1			T2	1		T7	5		T10	1
valid_sources[0x60]	30087	1			T7	3		T8	2		T10	13
valid_sources[0x61]	29921	1			T2	1		T7	7		T10	4
valid_sources[0x62]	34234	1			T2	1		T7	2		T11	5
valid_sources[0x63]	27924	1			T2	1		T7	5		T10	1
valid_sources[0x64]	26901	1			T2	1		T7	5		T11	11
valid_sources[0x65]	27152	1			T2	1		T11	3		T14	2
valid_sources[0x66]	28790	1			T2	1		T7	2		T10	1
valid_sources[0x67]	33465	1			T7	2		T10	2		T27	2
valid_sources[0x68]	29541	1			T2	1		T7	8		T8	1
valid_sources[0x69]	31585	1			T7	4		T10	3		T11	9
valid_sources[0x6a]	33170	1			T7	4		T10	7		T11	7
valid_sources[0x6b]	29244	1			T7	1		T27	1		T11	7
valid_sources[0x6c]	29366	1			T7	2		T10	1		T27	1
valid_sources[0x6d]	28238	1			T7	1		T10	5		T27	1
valid_sources[0x6e]	28389	1			T2	1		T7	2		T27	1
valid_sources[0x6f]	28114	1			T7	2		T8	1		T10	3
valid_sources[0x70]	27212	1			T7	6		T10	7		T11	6
valid_sources[0x71]	31586	1			T2	2		T7	1		T11	6
valid_sources[0x72]	29997	1			T7	6		T10	23		T11	9
valid_sources[0x73]	27783	1			T7	2		T10	1		T27	3
valid_sources[0x74]	26510	1			T7	2		T27	1		T11	4
valid_sources[0x75]	30859	1			T7	5		T10	9		T27	2
valid_sources[0x76]	26330	1			T7	7		T10	2		T27	3
valid_sources[0x77]	33883	1			T7	3		T8	1		T10	2
valid_sources[0x78]	31597	1			T7	3		T8	1		T11	5
valid_sources[0x79]	35813	1			T7	5		T10	11		T27	1
valid_sources[0x7a]	28501	1			T7	5		T10	2		T27	1
valid_sources[0x7b]	30129	1			T3	2		T7	3		T8	1
valid_sources[0x7c]	26890	1			T7	3		T8	1		T10	10
valid_sources[0x7d]	25979	1			T7	4		T8	1		T10	3
valid_sources[0x7e]	28215	1			T2	2		T7	2		T10	4
valid_sources[0x7f]	27279	1			T7	1		T11	5		T14	6
valid_sources[0x80]	29032	1			T7	5		T10	3		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1102983

1

T2

1

T4

5

T5

47

values[0x0]

all_enables

biggest_size

1559814

1

T4

50

T5

30

T7

430

values[0x1]

all_enables

biggest_size

1538467

1

T4

50

T5

22

T7

445