Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3600370

1

T1

1

T2

70

T3

2

full_word

4200764

1

T2

1

T5

99

T6

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7800704	1			T1	1		T2	71		T3	2
auto[TlIntgErrCmd]	151	1			T121	11		T122	14		T123	9
auto[TlIntgErrData]	144	1			T121	14		T122	5		T123	7
auto[TlIntgErrBoth]	135	1			T121	5		T122	11		T123	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4363311

1

T1

1

T2

71

T3

1

auto[1]

3437823

1

T3

1

T5

83

T6

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3259868	1			T1	1		T2	70		T3	1
auto[TlIntgErrNone]	partial	auto[1]	340110	1			T3	1		T5	31		T6	1
auto[TlIntgErrNone]	full_word	auto[0]	1103248	1			T2	1		T5	47		T6	1
auto[TlIntgErrNone]	full_word	auto[1]	3097478	1			T5	52		T7	875		T10	897
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T121	4		T122	5		T123	5
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T121	7		T122	8		T123	2
auto[TlIntgErrCmd]	full_word	auto[0]	10	1			T122	1		T123	1		T192	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T123	1		T195	1		T196	1
auto[TlIntgErrData]	partial	auto[0]	70	1			T121	9		T122	1		T123	3
auto[TlIntgErrData]	partial	auto[1]	60	1			T121	5		T122	3		T123	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T197	1		T196	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T122	1		T192	1		T195	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T121	2		T122	2		T123	2
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T121	3		T122	9		T123	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T192	1		T198	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T192	1		T182	1		T199	1