Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478272804	2769052	0	0
DepthKnown_A	478272804	478140440	0	0
RvalidKnown_A	478272804	478140440	0	0
WreadyKnown_A	478272804	478140440	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	2769052	0	0
T4	2958	100	0	0
T5	2312	0	0	0
T6	1396	0	0	0
T7	10337	832	0	0
T8	1711	0	0	0
T9	2928	0	0	0
T10	4250	1663	0	0
T11	17321	832	0	0
T12	8929	0	0	0
T13	0	832	0	0
T14	0	1671	0	0
T16	0	832	0	0
T18	0	1663	0	0
T19	0	832	0	0
T27	3415	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478272804	3088106	0	0
DepthKnown_A	478272804	478140440	0	0
RvalidKnown_A	478272804	478140440	0	0
WreadyKnown_A	478272804	478140440	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	3088106	0	0
T4	2958	454	0	0
T5	2312	0	0	0
T6	1396	0	0	0
T7	10337	3676	0	0
T8	1711	0	0	0
T9	2928	0	0	0
T10	4250	832	0	0
T11	17321	832	0	0
T12	8929	0	0	0
T13	0	832	0	0
T14	0	840	0	0
T16	0	3755	0	0
T18	0	832	0	0
T19	0	832	0	0
T27	3415	424	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478272804	190209	0	0
DepthKnown_A	478272804	478140440	0	0
RvalidKnown_A	478272804	478140440	0	0
WreadyKnown_A	478272804	478140440	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	190209	0	0
T4	2958	100	0	0
T5	2312	44	0	0
T6	1396	0	0	0
T7	10337	0	0	0
T8	1711	0	0	0
T9	2928	0	0	0
T10	4250	0	0	0
T11	17321	0	0	0
T12	8929	0	0	0
T15	0	8	0	0
T27	3415	100	0	0
T28	0	245	0	0
T32	0	11	0	0
T34	0	402	0	0
T43	0	100	0	0
T44	0	640	0	0
T45	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478272804	429207	0	0
DepthKnown_A	478272804	478140440	0	0
RvalidKnown_A	478272804	478140440	0	0
WreadyKnown_A	478272804	478140440	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	429207	0	0
T4	2958	426	0	0
T5	2312	44	0	0
T6	1396	0	0	0
T7	10337	0	0	0
T8	1711	0	0	0
T9	2928	0	0	0
T10	4250	0	0	0
T11	17321	0	0	0
T12	8929	0	0	0
T15	0	8	0	0
T27	3415	487	0	0
T28	0	245	0	0
T32	0	11	0	0
T34	0	402	0	0
T43	0	100	0	0
T44	0	2998	0	0
T45	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478272804	6245695	0	0
DepthKnown_A	478272804	478140440	0	0
RvalidKnown_A	478272804	478140440	0	0
WreadyKnown_A	478272804	478140440	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	6245695	0	0
T1	804	1	0	0
T2	1912	71	0	0
T3	1178	2	0	0
T4	2958	1	0	0
T5	2312	146	0	0
T6	1396	2	0	0
T7	10337	46	0	0
T8	1711	75	0	0
T9	2928	1	0	0
T10	4250	105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478272804	13248187	0	0
DepthKnown_A	478272804	478140440	0	0
RvalidKnown_A	478272804	478140440	0	0
WreadyKnown_A	478272804	478140440	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	13248187	0	0
T1	804	1	0	0
T2	1912	313	0	0
T3	1178	8	0	0
T4	2958	1	0	0
T5	2312	146	0	0
T6	1396	8	0	0
T7	10337	215	0	0
T8	1711	75	0	0
T9	2928	1	0	0
T10	4250	319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478272804	478140440	0	0
T1	804	712	0	0
T2	1912	1823	0	0
T3	1178	1124	0	0
T4	2958	2905	0	0
T5	2312	2227	0	0
T6	1396	1325	0	0
T7	10337	10252	0	0
T8	1711	1620	0	0
T9	2928	2013	0	0
T10	4250	4152	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0