Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
3703 |
0 |
0 |
T117 |
7511 |
176 |
0 |
0 |
T118 |
2274 |
3 |
0 |
0 |
T119 |
6660 |
247 |
0 |
0 |
T120 |
17181 |
273 |
0 |
0 |
T121 |
101754 |
1 |
0 |
0 |
T122 |
81814 |
5 |
0 |
0 |
T123 |
55392 |
2 |
0 |
0 |
T126 |
3523 |
38 |
0 |
0 |
T134 |
5005 |
4 |
0 |
0 |
T137 |
8923 |
7 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2228 |
0 |
0 |
T121 |
101754 |
111 |
0 |
0 |
T137 |
8923 |
17 |
0 |
0 |
T144 |
74440 |
497 |
0 |
0 |
T149 |
2901 |
6 |
0 |
0 |
T151 |
90813 |
261 |
0 |
0 |
T166 |
13996 |
55 |
0 |
0 |
T168 |
7627 |
37 |
0 |
0 |
T171 |
14671 |
72 |
0 |
0 |
T172 |
72891 |
521 |
0 |
0 |
T173 |
7457 |
3 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2064 |
0 |
0 |
T121 |
101754 |
116 |
0 |
0 |
T137 |
8923 |
10 |
0 |
0 |
T144 |
74440 |
475 |
0 |
0 |
T149 |
2901 |
4 |
0 |
0 |
T151 |
90813 |
273 |
0 |
0 |
T166 |
13996 |
43 |
0 |
0 |
T168 |
7627 |
10 |
0 |
0 |
T171 |
14671 |
43 |
0 |
0 |
T172 |
72891 |
443 |
0 |
0 |
T173 |
7457 |
7 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2638 |
0 |
0 |
T121 |
101754 |
216 |
0 |
0 |
T137 |
8923 |
33 |
0 |
0 |
T144 |
74440 |
505 |
0 |
0 |
T149 |
2901 |
4 |
0 |
0 |
T151 |
90813 |
204 |
0 |
0 |
T166 |
13996 |
56 |
0 |
0 |
T168 |
7627 |
23 |
0 |
0 |
T171 |
14671 |
56 |
0 |
0 |
T172 |
72891 |
437 |
0 |
0 |
T173 |
7457 |
8 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
10213 |
0 |
0 |
T121 |
101754 |
2092 |
0 |
0 |
T137 |
8923 |
13 |
0 |
0 |
T144 |
74440 |
502 |
0 |
0 |
T149 |
2901 |
120 |
0 |
0 |
T151 |
90813 |
259 |
0 |
0 |
T166 |
13996 |
38 |
0 |
0 |
T168 |
7627 |
36 |
0 |
0 |
T171 |
14671 |
28 |
0 |
0 |
T172 |
72891 |
461 |
0 |
0 |
T173 |
7457 |
150 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
11816 |
0 |
0 |
T121 |
101754 |
1837 |
0 |
0 |
T137 |
8923 |
126 |
0 |
0 |
T144 |
74440 |
476 |
0 |
0 |
T149 |
2901 |
5 |
0 |
0 |
T151 |
90813 |
250 |
0 |
0 |
T166 |
13996 |
89 |
0 |
0 |
T168 |
7627 |
26 |
0 |
0 |
T171 |
14671 |
44 |
0 |
0 |
T172 |
72891 |
449 |
0 |
0 |
T173 |
7457 |
70 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
12172 |
0 |
0 |
T121 |
101754 |
2287 |
0 |
0 |
T137 |
8923 |
81 |
0 |
0 |
T144 |
74440 |
478 |
0 |
0 |
T149 |
2901 |
9 |
0 |
0 |
T151 |
90813 |
188 |
0 |
0 |
T166 |
13996 |
65 |
0 |
0 |
T168 |
7627 |
48 |
0 |
0 |
T171 |
14671 |
53 |
0 |
0 |
T172 |
72891 |
462 |
0 |
0 |
T174 |
13358 |
52 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
9840 |
0 |
0 |
T121 |
101754 |
1454 |
0 |
0 |
T137 |
8923 |
69 |
0 |
0 |
T144 |
74440 |
518 |
0 |
0 |
T149 |
2901 |
128 |
0 |
0 |
T151 |
90813 |
250 |
0 |
0 |
T166 |
13996 |
47 |
0 |
0 |
T168 |
7627 |
36 |
0 |
0 |
T171 |
14671 |
25 |
0 |
0 |
T172 |
72891 |
464 |
0 |
0 |
T173 |
7457 |
6 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
10682 |
0 |
0 |
T121 |
101754 |
2023 |
0 |
0 |
T137 |
8923 |
7 |
0 |
0 |
T144 |
74440 |
491 |
0 |
0 |
T149 |
2901 |
4 |
0 |
0 |
T151 |
90813 |
269 |
0 |
0 |
T166 |
13996 |
56 |
0 |
0 |
T168 |
7627 |
19 |
0 |
0 |
T171 |
14671 |
56 |
0 |
0 |
T172 |
72891 |
437 |
0 |
0 |
T173 |
7457 |
147 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
12498 |
0 |
0 |
T121 |
101754 |
2327 |
0 |
0 |
T137 |
8923 |
7 |
0 |
0 |
T144 |
74440 |
432 |
0 |
0 |
T149 |
2901 |
93 |
0 |
0 |
T151 |
90813 |
229 |
0 |
0 |
T166 |
13996 |
35 |
0 |
0 |
T168 |
7627 |
6 |
0 |
0 |
T171 |
14671 |
53 |
0 |
0 |
T172 |
72891 |
445 |
0 |
0 |
T173 |
7457 |
67 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
10567 |
0 |
0 |
T121 |
101754 |
1951 |
0 |
0 |
T137 |
8923 |
64 |
0 |
0 |
T144 |
74440 |
568 |
0 |
0 |
T149 |
2901 |
7 |
0 |
0 |
T151 |
90813 |
215 |
0 |
0 |
T166 |
13996 |
34 |
0 |
0 |
T168 |
7627 |
22 |
0 |
0 |
T171 |
14671 |
26 |
0 |
0 |
T172 |
72891 |
484 |
0 |
0 |
T173 |
7457 |
96 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
10978 |
0 |
0 |
T121 |
101754 |
2197 |
0 |
0 |
T137 |
8923 |
125 |
0 |
0 |
T144 |
74440 |
508 |
0 |
0 |
T151 |
90813 |
249 |
0 |
0 |
T166 |
13996 |
64 |
0 |
0 |
T168 |
7627 |
43 |
0 |
0 |
T171 |
14671 |
42 |
0 |
0 |
T172 |
72891 |
542 |
0 |
0 |
T173 |
7457 |
126 |
0 |
0 |
T174 |
13358 |
49 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5452 |
0 |
0 |
T121 |
101754 |
922 |
0 |
0 |
T137 |
8923 |
8 |
0 |
0 |
T144 |
74440 |
457 |
0 |
0 |
T149 |
2901 |
46 |
0 |
0 |
T151 |
90813 |
258 |
0 |
0 |
T166 |
13996 |
65 |
0 |
0 |
T168 |
7627 |
8 |
0 |
0 |
T171 |
14671 |
52 |
0 |
0 |
T172 |
72891 |
436 |
0 |
0 |
T173 |
7457 |
32 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5035 |
0 |
0 |
T121 |
101754 |
552 |
0 |
0 |
T137 |
8923 |
57 |
0 |
0 |
T144 |
74440 |
484 |
0 |
0 |
T149 |
2901 |
45 |
0 |
0 |
T151 |
90813 |
203 |
0 |
0 |
T166 |
13996 |
49 |
0 |
0 |
T168 |
7627 |
33 |
0 |
0 |
T171 |
14671 |
48 |
0 |
0 |
T172 |
72891 |
437 |
0 |
0 |
T173 |
7457 |
68 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5597 |
0 |
0 |
T121 |
101754 |
1063 |
0 |
0 |
T137 |
8923 |
34 |
0 |
0 |
T144 |
74440 |
476 |
0 |
0 |
T149 |
2901 |
4 |
0 |
0 |
T151 |
90813 |
215 |
0 |
0 |
T166 |
13996 |
23 |
0 |
0 |
T168 |
7627 |
32 |
0 |
0 |
T171 |
14671 |
22 |
0 |
0 |
T172 |
72891 |
520 |
0 |
0 |
T173 |
7457 |
5 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5874 |
0 |
0 |
T121 |
101754 |
790 |
0 |
0 |
T137 |
8923 |
42 |
0 |
0 |
T144 |
74440 |
475 |
0 |
0 |
T149 |
2901 |
58 |
0 |
0 |
T151 |
90813 |
219 |
0 |
0 |
T166 |
13996 |
61 |
0 |
0 |
T168 |
7627 |
28 |
0 |
0 |
T171 |
14671 |
34 |
0 |
0 |
T172 |
72891 |
485 |
0 |
0 |
T173 |
7457 |
25 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5034 |
0 |
0 |
T121 |
101754 |
584 |
0 |
0 |
T137 |
8923 |
63 |
0 |
0 |
T144 |
74440 |
480 |
0 |
0 |
T149 |
2901 |
5 |
0 |
0 |
T151 |
90813 |
222 |
0 |
0 |
T166 |
13996 |
19 |
0 |
0 |
T168 |
7627 |
1 |
0 |
0 |
T171 |
14671 |
59 |
0 |
0 |
T172 |
72891 |
457 |
0 |
0 |
T173 |
7457 |
43 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5131 |
0 |
0 |
T121 |
101754 |
663 |
0 |
0 |
T137 |
8923 |
59 |
0 |
0 |
T144 |
74440 |
458 |
0 |
0 |
T149 |
2901 |
4 |
0 |
0 |
T151 |
90813 |
227 |
0 |
0 |
T166 |
13996 |
47 |
0 |
0 |
T168 |
7627 |
20 |
0 |
0 |
T171 |
14671 |
58 |
0 |
0 |
T172 |
72891 |
506 |
0 |
0 |
T173 |
7457 |
5 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5260 |
0 |
0 |
T121 |
101754 |
799 |
0 |
0 |
T137 |
8923 |
6 |
0 |
0 |
T144 |
74440 |
507 |
0 |
0 |
T149 |
2901 |
54 |
0 |
0 |
T151 |
90813 |
269 |
0 |
0 |
T166 |
13996 |
60 |
0 |
0 |
T168 |
7627 |
31 |
0 |
0 |
T171 |
14671 |
39 |
0 |
0 |
T172 |
72891 |
442 |
0 |
0 |
T173 |
7457 |
17 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5464 |
0 |
0 |
T121 |
101754 |
663 |
0 |
0 |
T137 |
8923 |
28 |
0 |
0 |
T144 |
74440 |
517 |
0 |
0 |
T149 |
2901 |
8 |
0 |
0 |
T151 |
90813 |
216 |
0 |
0 |
T166 |
13996 |
23 |
0 |
0 |
T168 |
7627 |
21 |
0 |
0 |
T171 |
14671 |
53 |
0 |
0 |
T172 |
72891 |
476 |
0 |
0 |
T173 |
7457 |
27 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5631 |
0 |
0 |
T121 |
101754 |
817 |
0 |
0 |
T137 |
8923 |
69 |
0 |
0 |
T144 |
74440 |
552 |
0 |
0 |
T149 |
2901 |
2 |
0 |
0 |
T151 |
90813 |
244 |
0 |
0 |
T166 |
13996 |
42 |
0 |
0 |
T168 |
7627 |
35 |
0 |
0 |
T171 |
14671 |
46 |
0 |
0 |
T172 |
72891 |
459 |
0 |
0 |
T173 |
7457 |
27 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5597 |
0 |
0 |
T121 |
101754 |
892 |
0 |
0 |
T137 |
8923 |
6 |
0 |
0 |
T144 |
74440 |
471 |
0 |
0 |
T149 |
2901 |
38 |
0 |
0 |
T151 |
90813 |
189 |
0 |
0 |
T166 |
13996 |
92 |
0 |
0 |
T168 |
7627 |
34 |
0 |
0 |
T171 |
14671 |
77 |
0 |
0 |
T172 |
72891 |
451 |
0 |
0 |
T173 |
7457 |
6 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5839 |
0 |
0 |
T121 |
101754 |
1021 |
0 |
0 |
T137 |
8923 |
59 |
0 |
0 |
T144 |
74440 |
501 |
0 |
0 |
T149 |
2901 |
5 |
0 |
0 |
T151 |
90813 |
255 |
0 |
0 |
T166 |
13996 |
57 |
0 |
0 |
T168 |
7627 |
19 |
0 |
0 |
T171 |
14671 |
60 |
0 |
0 |
T172 |
72891 |
425 |
0 |
0 |
T173 |
7457 |
31 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5530 |
0 |
0 |
T121 |
101754 |
848 |
0 |
0 |
T137 |
8923 |
2 |
0 |
0 |
T144 |
74440 |
507 |
0 |
0 |
T149 |
2901 |
3 |
0 |
0 |
T151 |
90813 |
248 |
0 |
0 |
T166 |
13996 |
27 |
0 |
0 |
T168 |
7627 |
36 |
0 |
0 |
T171 |
14671 |
35 |
0 |
0 |
T172 |
72891 |
492 |
0 |
0 |
T173 |
7457 |
25 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5702 |
0 |
0 |
T121 |
101754 |
818 |
0 |
0 |
T137 |
8923 |
33 |
0 |
0 |
T144 |
74440 |
454 |
0 |
0 |
T149 |
2901 |
1 |
0 |
0 |
T151 |
90813 |
193 |
0 |
0 |
T166 |
13996 |
49 |
0 |
0 |
T168 |
7627 |
43 |
0 |
0 |
T171 |
14671 |
41 |
0 |
0 |
T172 |
72891 |
482 |
0 |
0 |
T173 |
7457 |
16 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5760 |
0 |
0 |
T121 |
101754 |
686 |
0 |
0 |
T137 |
8923 |
32 |
0 |
0 |
T144 |
74440 |
479 |
0 |
0 |
T151 |
90813 |
224 |
0 |
0 |
T166 |
13996 |
72 |
0 |
0 |
T168 |
7627 |
50 |
0 |
0 |
T171 |
14671 |
37 |
0 |
0 |
T172 |
72891 |
476 |
0 |
0 |
T173 |
7457 |
55 |
0 |
0 |
T174 |
13358 |
78 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5970 |
0 |
0 |
T121 |
101754 |
849 |
0 |
0 |
T128 |
19054 |
8 |
0 |
0 |
T137 |
8923 |
9 |
0 |
0 |
T144 |
74440 |
508 |
0 |
0 |
T151 |
90813 |
198 |
0 |
0 |
T166 |
13996 |
77 |
0 |
0 |
T168 |
7627 |
16 |
0 |
0 |
T171 |
14671 |
68 |
0 |
0 |
T172 |
72891 |
472 |
0 |
0 |
T173 |
7457 |
26 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5706 |
0 |
0 |
T121 |
101754 |
892 |
0 |
0 |
T137 |
8923 |
76 |
0 |
0 |
T144 |
74440 |
476 |
0 |
0 |
T151 |
90813 |
198 |
0 |
0 |
T166 |
13996 |
28 |
0 |
0 |
T168 |
7627 |
2 |
0 |
0 |
T171 |
14671 |
50 |
0 |
0 |
T172 |
72891 |
491 |
0 |
0 |
T173 |
7457 |
1 |
0 |
0 |
T174 |
13358 |
45 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
4848 |
0 |
0 |
T121 |
101754 |
608 |
0 |
0 |
T137 |
8923 |
23 |
0 |
0 |
T144 |
74440 |
462 |
0 |
0 |
T149 |
2901 |
4 |
0 |
0 |
T151 |
90813 |
199 |
0 |
0 |
T166 |
13996 |
34 |
0 |
0 |
T168 |
7627 |
34 |
0 |
0 |
T171 |
14671 |
53 |
0 |
0 |
T172 |
72891 |
414 |
0 |
0 |
T173 |
7457 |
32 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5780 |
0 |
0 |
T121 |
101754 |
873 |
0 |
0 |
T137 |
8923 |
9 |
0 |
0 |
T144 |
74440 |
524 |
0 |
0 |
T149 |
2901 |
5 |
0 |
0 |
T151 |
90813 |
235 |
0 |
0 |
T166 |
13996 |
68 |
0 |
0 |
T168 |
7627 |
14 |
0 |
0 |
T171 |
14671 |
60 |
0 |
0 |
T172 |
72891 |
475 |
0 |
0 |
T173 |
7457 |
35 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5127 |
0 |
0 |
T121 |
101754 |
675 |
0 |
0 |
T137 |
8923 |
31 |
0 |
0 |
T144 |
74440 |
526 |
0 |
0 |
T149 |
2901 |
6 |
0 |
0 |
T151 |
90813 |
228 |
0 |
0 |
T166 |
13996 |
36 |
0 |
0 |
T168 |
7627 |
5 |
0 |
0 |
T171 |
14671 |
38 |
0 |
0 |
T172 |
72891 |
492 |
0 |
0 |
T173 |
7457 |
24 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5556 |
0 |
0 |
T121 |
101754 |
683 |
0 |
0 |
T137 |
8923 |
61 |
0 |
0 |
T144 |
74440 |
551 |
0 |
0 |
T149 |
2901 |
9 |
0 |
0 |
T151 |
90813 |
247 |
0 |
0 |
T166 |
13996 |
68 |
0 |
0 |
T168 |
7627 |
20 |
0 |
0 |
T171 |
14671 |
50 |
0 |
0 |
T172 |
72891 |
455 |
0 |
0 |
T173 |
7457 |
13 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5885 |
0 |
0 |
T121 |
101754 |
1045 |
0 |
0 |
T137 |
8923 |
38 |
0 |
0 |
T144 |
74440 |
494 |
0 |
0 |
T149 |
2901 |
27 |
0 |
0 |
T151 |
90813 |
227 |
0 |
0 |
T166 |
13996 |
43 |
0 |
0 |
T168 |
7627 |
39 |
0 |
0 |
T171 |
14671 |
28 |
0 |
0 |
T172 |
72891 |
487 |
0 |
0 |
T173 |
7457 |
53 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5334 |
0 |
0 |
T121 |
101754 |
734 |
0 |
0 |
T137 |
8923 |
58 |
0 |
0 |
T144 |
74440 |
519 |
0 |
0 |
T149 |
2901 |
52 |
0 |
0 |
T151 |
90813 |
250 |
0 |
0 |
T166 |
13996 |
60 |
0 |
0 |
T168 |
7627 |
27 |
0 |
0 |
T171 |
14671 |
49 |
0 |
0 |
T172 |
72891 |
468 |
0 |
0 |
T173 |
7457 |
24 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5664 |
0 |
0 |
T121 |
101754 |
915 |
0 |
0 |
T137 |
8923 |
37 |
0 |
0 |
T144 |
74440 |
474 |
0 |
0 |
T151 |
90813 |
234 |
0 |
0 |
T166 |
13996 |
45 |
0 |
0 |
T168 |
7627 |
2 |
0 |
0 |
T171 |
14671 |
46 |
0 |
0 |
T172 |
72891 |
489 |
0 |
0 |
T173 |
7457 |
57 |
0 |
0 |
T174 |
13358 |
60 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5439 |
0 |
0 |
T121 |
101754 |
881 |
0 |
0 |
T137 |
8923 |
7 |
0 |
0 |
T144 |
74440 |
553 |
0 |
0 |
T149 |
2901 |
3 |
0 |
0 |
T151 |
90813 |
256 |
0 |
0 |
T166 |
13996 |
48 |
0 |
0 |
T168 |
7627 |
8 |
0 |
0 |
T171 |
14671 |
47 |
0 |
0 |
T172 |
72891 |
448 |
0 |
0 |
T173 |
7457 |
9 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2329 |
0 |
0 |
T121 |
101754 |
169 |
0 |
0 |
T137 |
8923 |
16 |
0 |
0 |
T144 |
74440 |
511 |
0 |
0 |
T149 |
2901 |
3 |
0 |
0 |
T151 |
90813 |
201 |
0 |
0 |
T166 |
13996 |
78 |
0 |
0 |
T168 |
7627 |
6 |
0 |
0 |
T171 |
14671 |
26 |
0 |
0 |
T172 |
72891 |
465 |
0 |
0 |
T173 |
7457 |
8 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2388 |
0 |
0 |
T121 |
101754 |
135 |
0 |
0 |
T137 |
8923 |
13 |
0 |
0 |
T144 |
74440 |
481 |
0 |
0 |
T149 |
2901 |
2 |
0 |
0 |
T151 |
90813 |
264 |
0 |
0 |
T166 |
13996 |
62 |
0 |
0 |
T168 |
7627 |
18 |
0 |
0 |
T171 |
14671 |
53 |
0 |
0 |
T172 |
72891 |
491 |
0 |
0 |
T173 |
7457 |
7 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2320 |
0 |
0 |
T121 |
101754 |
145 |
0 |
0 |
T137 |
8923 |
11 |
0 |
0 |
T144 |
74440 |
559 |
0 |
0 |
T149 |
2901 |
3 |
0 |
0 |
T151 |
90813 |
211 |
0 |
0 |
T166 |
13996 |
23 |
0 |
0 |
T168 |
7627 |
1 |
0 |
0 |
T171 |
14671 |
61 |
0 |
0 |
T172 |
72891 |
516 |
0 |
0 |
T173 |
7457 |
4 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2441 |
0 |
0 |
T121 |
101754 |
186 |
0 |
0 |
T137 |
8923 |
11 |
0 |
0 |
T144 |
74440 |
472 |
0 |
0 |
T149 |
2901 |
7 |
0 |
0 |
T151 |
90813 |
238 |
0 |
0 |
T166 |
13996 |
60 |
0 |
0 |
T168 |
7627 |
30 |
0 |
0 |
T171 |
14671 |
55 |
0 |
0 |
T172 |
72891 |
457 |
0 |
0 |
T173 |
7457 |
4 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2937 |
0 |
0 |
T121 |
101754 |
336 |
0 |
0 |
T137 |
8923 |
13 |
0 |
0 |
T144 |
74440 |
533 |
0 |
0 |
T149 |
2901 |
2 |
0 |
0 |
T151 |
90813 |
222 |
0 |
0 |
T166 |
13996 |
101 |
0 |
0 |
T168 |
7627 |
13 |
0 |
0 |
T171 |
14671 |
35 |
0 |
0 |
T172 |
72891 |
430 |
0 |
0 |
T173 |
7457 |
12 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
5165 |
0 |
0 |
T24 |
3890 |
33 |
0 |
0 |
T25 |
4076 |
0 |
0 |
0 |
T38 |
0 |
23 |
0 |
0 |
T39 |
0 |
40 |
0 |
0 |
T44 |
600509 |
0 |
0 |
0 |
T45 |
1581 |
0 |
0 |
0 |
T51 |
102392 |
0 |
0 |
0 |
T59 |
149339 |
0 |
0 |
0 |
T94 |
765 |
0 |
0 |
0 |
T96 |
0 |
76 |
0 |
0 |
T102 |
155911 |
0 |
0 |
0 |
T156 |
0 |
17 |
0 |
0 |
T175 |
0 |
12 |
0 |
0 |
T176 |
0 |
17 |
0 |
0 |
T177 |
0 |
42 |
0 |
0 |
T178 |
0 |
57 |
0 |
0 |
T179 |
0 |
41 |
0 |
0 |
T180 |
1815 |
0 |
0 |
0 |
T181 |
790 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2268 |
0 |
0 |
T121 |
101754 |
178 |
0 |
0 |
T137 |
8923 |
1 |
0 |
0 |
T144 |
74440 |
506 |
0 |
0 |
T149 |
2901 |
5 |
0 |
0 |
T151 |
90813 |
214 |
0 |
0 |
T166 |
13996 |
4 |
0 |
0 |
T168 |
7627 |
46 |
0 |
0 |
T171 |
14671 |
52 |
0 |
0 |
T172 |
72891 |
466 |
0 |
0 |
T173 |
7457 |
2 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2271 |
0 |
0 |
T121 |
101754 |
134 |
0 |
0 |
T137 |
8923 |
13 |
0 |
0 |
T144 |
74440 |
494 |
0 |
0 |
T149 |
2901 |
5 |
0 |
0 |
T151 |
90813 |
224 |
0 |
0 |
T166 |
13996 |
39 |
0 |
0 |
T168 |
7627 |
11 |
0 |
0 |
T171 |
14671 |
33 |
0 |
0 |
T172 |
72891 |
454 |
0 |
0 |
T173 |
7457 |
12 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2145 |
0 |
0 |
T121 |
101754 |
107 |
0 |
0 |
T137 |
8923 |
12 |
0 |
0 |
T144 |
74440 |
564 |
0 |
0 |
T149 |
2901 |
9 |
0 |
0 |
T151 |
90813 |
205 |
0 |
0 |
T166 |
13996 |
64 |
0 |
0 |
T168 |
7627 |
20 |
0 |
0 |
T171 |
14671 |
54 |
0 |
0 |
T172 |
72891 |
486 |
0 |
0 |
T173 |
7457 |
15 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2105 |
0 |
0 |
T121 |
101754 |
116 |
0 |
0 |
T137 |
8923 |
18 |
0 |
0 |
T144 |
74440 |
525 |
0 |
0 |
T149 |
2901 |
4 |
0 |
0 |
T151 |
90813 |
214 |
0 |
0 |
T166 |
13996 |
39 |
0 |
0 |
T168 |
7627 |
39 |
0 |
0 |
T171 |
14671 |
27 |
0 |
0 |
T172 |
72891 |
498 |
0 |
0 |
T174 |
13358 |
44 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2244 |
0 |
0 |
T121 |
101754 |
118 |
0 |
0 |
T137 |
8923 |
4 |
0 |
0 |
T144 |
74440 |
552 |
0 |
0 |
T151 |
90813 |
250 |
0 |
0 |
T166 |
13996 |
44 |
0 |
0 |
T168 |
7627 |
5 |
0 |
0 |
T171 |
14671 |
59 |
0 |
0 |
T172 |
72891 |
437 |
0 |
0 |
T174 |
13358 |
28 |
0 |
0 |
T182 |
97661 |
155 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2096 |
0 |
0 |
T121 |
101754 |
85 |
0 |
0 |
T128 |
19054 |
5 |
0 |
0 |
T137 |
8923 |
10 |
0 |
0 |
T144 |
74440 |
486 |
0 |
0 |
T149 |
2901 |
1 |
0 |
0 |
T151 |
90813 |
226 |
0 |
0 |
T166 |
13996 |
58 |
0 |
0 |
T168 |
7627 |
30 |
0 |
0 |
T171 |
14671 |
17 |
0 |
0 |
T172 |
72891 |
448 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2892 |
0 |
0 |
T121 |
101754 |
269 |
0 |
0 |
T137 |
8923 |
12 |
0 |
0 |
T144 |
74440 |
518 |
0 |
0 |
T151 |
90813 |
252 |
0 |
0 |
T166 |
13996 |
45 |
0 |
0 |
T168 |
7627 |
29 |
0 |
0 |
T171 |
14671 |
24 |
0 |
0 |
T172 |
72891 |
436 |
0 |
0 |
T173 |
7457 |
13 |
0 |
0 |
T174 |
13358 |
13 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2191 |
0 |
0 |
T121 |
101754 |
109 |
0 |
0 |
T137 |
8923 |
5 |
0 |
0 |
T144 |
74440 |
525 |
0 |
0 |
T149 |
2901 |
4 |
0 |
0 |
T151 |
90813 |
197 |
0 |
0 |
T166 |
13996 |
109 |
0 |
0 |
T168 |
7627 |
6 |
0 |
0 |
T171 |
14671 |
39 |
0 |
0 |
T172 |
72891 |
515 |
0 |
0 |
T174 |
13358 |
50 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
3216 |
0 |
0 |
T121 |
101754 |
418 |
0 |
0 |
T137 |
8923 |
21 |
0 |
0 |
T144 |
74440 |
479 |
0 |
0 |
T149 |
2901 |
6 |
0 |
0 |
T151 |
90813 |
221 |
0 |
0 |
T166 |
13996 |
76 |
0 |
0 |
T168 |
7627 |
12 |
0 |
0 |
T171 |
14671 |
60 |
0 |
0 |
T172 |
72891 |
533 |
0 |
0 |
T174 |
13358 |
56 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2470 |
0 |
0 |
T121 |
101754 |
224 |
0 |
0 |
T137 |
8923 |
7 |
0 |
0 |
T144 |
74440 |
463 |
0 |
0 |
T149 |
2901 |
7 |
0 |
0 |
T151 |
90813 |
220 |
0 |
0 |
T166 |
13996 |
69 |
0 |
0 |
T168 |
7627 |
4 |
0 |
0 |
T171 |
14671 |
22 |
0 |
0 |
T172 |
72891 |
483 |
0 |
0 |
T173 |
7457 |
20 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2061 |
0 |
0 |
T121 |
101754 |
141 |
0 |
0 |
T128 |
19054 |
9 |
0 |
0 |
T137 |
8923 |
3 |
0 |
0 |
T144 |
74440 |
460 |
0 |
0 |
T149 |
2901 |
2 |
0 |
0 |
T151 |
90813 |
242 |
0 |
0 |
T166 |
13996 |
18 |
0 |
0 |
T168 |
7627 |
39 |
0 |
0 |
T171 |
14671 |
42 |
0 |
0 |
T172 |
72891 |
468 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2086 |
0 |
0 |
T121 |
101754 |
117 |
0 |
0 |
T137 |
8923 |
7 |
0 |
0 |
T144 |
74440 |
494 |
0 |
0 |
T149 |
2901 |
8 |
0 |
0 |
T151 |
90813 |
208 |
0 |
0 |
T166 |
13996 |
61 |
0 |
0 |
T168 |
7627 |
29 |
0 |
0 |
T171 |
14671 |
43 |
0 |
0 |
T172 |
72891 |
432 |
0 |
0 |
T173 |
7457 |
1 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2157 |
0 |
0 |
T121 |
101754 |
111 |
0 |
0 |
T137 |
8923 |
12 |
0 |
0 |
T144 |
74440 |
487 |
0 |
0 |
T149 |
2901 |
9 |
0 |
0 |
T151 |
90813 |
199 |
0 |
0 |
T166 |
13996 |
67 |
0 |
0 |
T168 |
7627 |
23 |
0 |
0 |
T171 |
14671 |
28 |
0 |
0 |
T172 |
72891 |
483 |
0 |
0 |
T174 |
13358 |
59 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2062 |
0 |
0 |
T121 |
101754 |
110 |
0 |
0 |
T137 |
8923 |
9 |
0 |
0 |
T144 |
74440 |
499 |
0 |
0 |
T149 |
2901 |
1 |
0 |
0 |
T151 |
90813 |
219 |
0 |
0 |
T166 |
13996 |
49 |
0 |
0 |
T168 |
7627 |
1 |
0 |
0 |
T171 |
14671 |
48 |
0 |
0 |
T172 |
72891 |
525 |
0 |
0 |
T173 |
7457 |
7 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2198 |
0 |
0 |
T121 |
101754 |
149 |
0 |
0 |
T137 |
8923 |
26 |
0 |
0 |
T144 |
74440 |
592 |
0 |
0 |
T149 |
2901 |
1 |
0 |
0 |
T151 |
90813 |
258 |
0 |
0 |
T166 |
13996 |
37 |
0 |
0 |
T168 |
7627 |
8 |
0 |
0 |
T171 |
14671 |
36 |
0 |
0 |
T172 |
72891 |
467 |
0 |
0 |
T173 |
7457 |
7 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
478272804 |
2171 |
0 |
0 |
T121 |
101754 |
120 |
0 |
0 |
T137 |
8923 |
13 |
0 |
0 |
T144 |
74440 |
481 |
0 |
0 |
T149 |
2901 |
6 |
0 |
0 |
T151 |
90813 |
209 |
0 |
0 |
T166 |
13996 |
44 |
0 |
0 |
T168 |
7627 |
61 |
0 |
0 |
T172 |
72891 |
532 |
0 |
0 |
T173 |
7457 |
3 |
0 |
0 |
T174 |
13358 |
48 |
0 |
0 |