Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3806507	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4296383

1

T1

1

T2

108

T4

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4516873	1			T1	67		T2	101		T3	1
values[0x0]	1792220	1			T2	53		T4	18		T5	43
values[0x1]	1793797	1			T2	47		T4	7		T5	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2693295	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5409595

1

T1

19

T2

164

T4

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29953	1			T1	1		T6	4		T8	6
valid_sources[0x01]	30797	1			T2	1		T6	3		T7	1417
valid_sources[0x02]	29188	1			T2	2		T8	3		T9	8
valid_sources[0x03]	29932	1			T4	2		T5	1		T8	2
valid_sources[0x04]	33111	1			T6	1		T8	3		T9	3
valid_sources[0x05]	28218	1			T1	2		T8	3		T9	18
valid_sources[0x06]	32095	1			T5	1		T6	1		T8	1
valid_sources[0x07]	35646	1			T6	2		T7	4		T8	4
valid_sources[0x08]	32204	1			T6	2		T8	3		T9	14
valid_sources[0x09]	31559	1			T4	4		T5	1		T6	4
valid_sources[0x0a]	32104	1			T2	1		T6	4		T8	2
valid_sources[0x0b]	33930	1			T2	4		T6	1		T8	2
valid_sources[0x0c]	31181	1			T6	3		T8	2		T9	20
valid_sources[0x0d]	31333	1			T6	2		T8	7		T9	5
valid_sources[0x0e]	28314	1			T6	2		T8	4		T9	7
valid_sources[0x0f]	35560	1			T6	2		T8	5		T9	4
valid_sources[0x10]	29602	1			T8	3		T9	5		T10	3
valid_sources[0x11]	32472	1			T2	1		T8	3		T9	1
valid_sources[0x12]	33946	1			T5	1		T7	14		T8	6
valid_sources[0x13]	33568	1			T6	2		T8	1		T9	5
valid_sources[0x14]	30533	1			T5	1		T6	1		T8	2
valid_sources[0x15]	30410	1			T6	2		T8	2		T9	10
valid_sources[0x16]	31710	1			T8	10		T9	5		T10	6
valid_sources[0x17]	31962	1			T6	2		T8	3		T9	8
valid_sources[0x18]	30037	1			T2	1		T6	1		T7	4
valid_sources[0x19]	29487	1			T1	1		T2	1		T6	4
valid_sources[0x1a]	42882	1			T6	1		T9	9		T10	2
valid_sources[0x1b]	29478	1			T6	1		T8	7		T9	5
valid_sources[0x1c]	30641	1			T1	1		T2	2		T6	4
valid_sources[0x1d]	28050	1			T1	1		T8	7		T9	3
valid_sources[0x1e]	30161	1			T2	1		T6	2		T8	8
valid_sources[0x1f]	30930	1			T1	2		T2	1		T8	2
valid_sources[0x20]	28813	1			T1	2		T6	1		T8	8
valid_sources[0x21]	30797	1			T1	2		T6	1		T8	5
valid_sources[0x22]	36070	1			T6	1		T8	4		T9	8
valid_sources[0x23]	33488	1			T2	1		T6	2		T9	6
valid_sources[0x24]	30429	1			T2	4		T5	1		T6	3
valid_sources[0x25]	33241	1			T2	1		T5	1		T10	5
valid_sources[0x26]	29046	1			T6	2		T8	3		T9	9
valid_sources[0x27]	31517	1			T1	1		T2	1		T6	1
valid_sources[0x28]	36689	1			T2	3		T5	1		T6	2
valid_sources[0x29]	30486	1			T5	1		T8	3		T9	5
valid_sources[0x2a]	31223	1			T1	1		T5	1		T6	2
valid_sources[0x2b]	29583	1			T2	1		T6	2		T8	1
valid_sources[0x2c]	30430	1			T1	1		T2	3		T6	3
valid_sources[0x2d]	31087	1			T6	4		T8	1		T9	4
valid_sources[0x2e]	29950	1			T5	3		T6	1		T8	2
valid_sources[0x2f]	29609	1			T5	2		T6	2		T8	7
valid_sources[0x30]	34004	1			T2	1		T5	1		T6	3
valid_sources[0x31]	29076	1			T2	1		T6	5		T8	2
valid_sources[0x32]	32257	1			T5	1		T6	3		T8	4
valid_sources[0x33]	31067	1			T2	4		T5	1		T8	1
valid_sources[0x34]	34027	1			T6	3		T8	4		T9	5
valid_sources[0x35]	27708	1			T6	2		T7	1		T8	2
valid_sources[0x36]	32737	1			T5	2		T6	3		T8	3
valid_sources[0x37]	29716	1			T6	4		T8	4		T9	2
valid_sources[0x38]	28850	1			T5	1		T6	1		T8	5
valid_sources[0x39]	30300	1			T6	3		T8	6		T9	1
valid_sources[0x3a]	47068	1			T2	1		T6	2		T9	1
valid_sources[0x3b]	30540	1			T1	1		T2	2		T6	2
valid_sources[0x3c]	32852	1			T2	2		T5	1		T9	6
valid_sources[0x3d]	48912	1			T1	1		T7	893		T8	5
valid_sources[0x3e]	29162	1			T2	2		T5	1		T8	4
valid_sources[0x3f]	32826	1			T6	1		T9	7		T10	4
valid_sources[0x40]	28744	1			T1	2		T5	1		T6	1
valid_sources[0x41]	39775	1			T1	1		T5	3		T6	2
valid_sources[0x42]	29830	1			T5	1		T6	1		T7	2
valid_sources[0x43]	29456	1			T1	1		T2	2		T6	1
valid_sources[0x44]	29905	1			T1	1		T6	6		T8	4
valid_sources[0x45]	31384	1			T6	7		T8	8		T9	12
valid_sources[0x46]	29424	1			T6	1		T8	1		T9	13
valid_sources[0x47]	32638	1			T2	1		T5	1		T8	3
valid_sources[0x48]	30194	1			T6	2		T8	3		T9	16
valid_sources[0x49]	27849	1			T1	1		T2	2		T4	2
valid_sources[0x4a]	33024	1			T2	1		T5	1		T6	2
valid_sources[0x4b]	34915	1			T2	3		T6	3		T8	3
valid_sources[0x4c]	33347	1			T2	1		T8	6		T9	21
valid_sources[0x4d]	28777	1			T1	2		T2	4		T5	1
valid_sources[0x4e]	28351	1			T5	1		T6	3		T8	1
valid_sources[0x4f]	32075	1			T1	1		T6	5		T8	9
valid_sources[0x50]	30821	1			T1	1		T6	4		T8	5
valid_sources[0x51]	28361	1			T1	2		T6	3		T8	2
valid_sources[0x52]	29927	1			T2	2		T6	3		T9	13
valid_sources[0x53]	33747	1			T5	1		T6	3		T9	21
valid_sources[0x54]	29020	1			T1	1		T6	2		T9	9
valid_sources[0x55]	32577	1			T2	3		T6	4		T9	4
valid_sources[0x56]	34801	1			T2	1		T6	3		T8	5
valid_sources[0x57]	28095	1			T6	2		T8	3		T9	11
valid_sources[0x58]	28392	1			T2	2		T6	2		T8	10
valid_sources[0x59]	30991	1			T2	1		T6	3		T8	1
valid_sources[0x5a]	31044	1			T1	2		T2	1		T6	2
valid_sources[0x5b]	29835	1			T2	1		T8	4		T9	4
valid_sources[0x5c]	28026	1			T2	5		T5	1		T8	5
valid_sources[0x5d]	28493	1			T1	2		T2	1		T6	1
valid_sources[0x5e]	29674	1			T6	2		T8	3		T9	3
valid_sources[0x5f]	30515	1			T2	2		T5	1		T6	3
valid_sources[0x60]	30721	1			T6	1		T8	6		T9	10
valid_sources[0x61]	27615	1			T2	1		T6	1		T8	4
valid_sources[0x62]	36809	1			T2	1		T6	7		T8	2
valid_sources[0x63]	34243	1			T2	1		T5	1		T6	2
valid_sources[0x64]	28758	1			T1	2		T2	2		T6	3
valid_sources[0x65]	30373	1			T2	1		T6	3		T8	3
valid_sources[0x66]	27615	1			T8	3		T9	10		T10	5
valid_sources[0x67]	30901	1			T6	3		T8	3		T9	15
valid_sources[0x68]	28376	1			T2	1		T6	4		T8	5
valid_sources[0x69]	37528	1			T2	2		T8	6		T10	4
valid_sources[0x6a]	28953	1			T1	1		T6	5		T8	6
valid_sources[0x6b]	31021	1			T2	1		T6	3		T8	3
valid_sources[0x6c]	29213	1			T6	2		T8	2		T9	2
valid_sources[0x6d]	30843	1			T6	1		T8	5		T9	9
valid_sources[0x6e]	27452	1			T5	1		T8	4		T9	2
valid_sources[0x6f]	28761	1			T6	3		T8	3		T9	7
valid_sources[0x70]	30140	1			T2	2		T6	3		T8	2
valid_sources[0x71]	28367	1			T2	3		T6	1		T8	3
valid_sources[0x72]	30675	1			T5	1		T6	1		T8	2
valid_sources[0x73]	30711	1			T6	2		T8	1		T9	14
valid_sources[0x74]	33835	1			T6	1		T8	12		T9	17
valid_sources[0x75]	32850	1			T6	1		T8	2		T9	12
valid_sources[0x76]	29196	1			T2	3		T6	3		T8	2
valid_sources[0x77]	30656	1			T6	2		T8	1		T9	5
valid_sources[0x78]	31744	1			T1	1		T5	1		T6	3
valid_sources[0x79]	40561	1			T8	5		T9	3		T10	8
valid_sources[0x7a]	29598	1			T6	4		T8	4		T9	3
valid_sources[0x7b]	48255	1			T2	2		T6	2		T8	5
valid_sources[0x7c]	31054	1			T5	2		T6	5		T8	4
valid_sources[0x7d]	37990	1			T2	1		T5	1		T6	3
valid_sources[0x7e]	29233	1			T6	6		T8	2		T9	13
valid_sources[0x7f]	32655	1			T2	1		T6	3		T8	6
valid_sources[0x80]	28167	1			T6	1		T8	3		T9	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1056961

1

T1

1

T2

8

T4

1

values[0x0]

all_enables

biggest_size

1630971

1

T2

53

T4

15

T5

36

values[0x1]

all_enables

biggest_size

1608451

1

T2

47

T4

5

T5

34