Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3828030

1

T1

66

T3

1

T4

5

full_word

4295683

1

T1

1

T4

21

T5

70

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8123303	1			T1	67		T3	1		T4	26
auto[TlIntgErrCmd]	134	1			T118	2		T122	1		T123	9
auto[TlIntgErrData]	124	1			T118	7		T122	13		T123	8
auto[TlIntgErrBoth]	152	1			T118	1		T122	6		T123	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4520053

1

T1

67

T3

1

T4

1

auto[1]

3603660

1

T4

25

T5

85

T6

61

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3462698	1			T1	66		T3	1		T5	1
auto[TlIntgErrNone]	partial	auto[1]	364959	1			T4	5		T5	15		T6	19
auto[TlIntgErrNone]	full_word	auto[0]	1057190	1			T1	1		T4	1		T6	21
auto[TlIntgErrNone]	full_word	auto[1]	3238456	1			T4	20		T5	70		T6	42
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T118	1		T122	1		T123	4
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T118	1		T123	5		T201	8
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T204	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T130	2		T205	1		T206	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T118	5		T122	5		T123	4
auto[TlIntgErrData]	partial	auto[1]	61	1			T118	2		T122	5		T123	4
auto[TlIntgErrData]	full_word	auto[0]	9	1			T122	2		T201	2		T130	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T122	1		T207	1		T208	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T122	1		T123	4		T201	3
auto[TlIntgErrBoth]	partial	auto[1]	89	1			T118	1		T122	5		T123	7
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T130	1		T207	2		T203	2
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T123	2		T201	2		T130	2