Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	472825360	2800632	0	0
DepthKnown_A	472825360	472689929	0	0
RvalidKnown_A	472825360	472689929	0	0
WreadyKnown_A	472825360	472689929	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	2800632	0	0
T2	2099	100	0	0
T3	1462	0	0	0
T4	2459	0	0	0
T5	13662	0	0	0
T6	11901	0	0	0
T7	130782	0	0	0
T8	33680	832	0	0
T9	26037	2183	0	0
T10	358623	1663	0	0
T11	25086	832	0	0
T12	0	1663	0	0
T16	0	1663	0	0
T17	0	1663	0	0
T18	0	1663	0	0
T39	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	472825360	3147279	0	0
DepthKnown_A	472825360	472689929	0	0
RvalidKnown_A	472825360	472689929	0	0
WreadyKnown_A	472825360	472689929	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	3147279	0	0
T2	2099	100	0	0
T3	1462	0	0	0
T4	2459	0	0	0
T5	13662	0	0	0
T6	11901	0	0	0
T7	130782	0	0	0
T8	33680	2607	0	0
T9	26037	1098	0	0
T10	358623	832	0	0
T11	25086	832	0	0
T12	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T18	0	832	0	0
T39	0	437	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	472825360	193312	0	0
DepthKnown_A	472825360	472689929	0	0
RvalidKnown_A	472825360	472689929	0	0
WreadyKnown_A	472825360	472689929	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	193312	0	0
T2	2099	100	0	0
T3	1462	0	0	0
T4	2459	0	0	0
T5	13662	0	0	0
T6	11901	18	0	0
T7	130782	192	0	0
T8	33680	0	0	0
T9	26037	0	0	0
T10	358623	0	0	0
T11	25086	64	0	0
T25	0	1	0	0
T28	0	35	0	0
T29	0	448	0	0
T39	0	100	0	0
T41	0	100	0	0
T42	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	472825360	435866	0	0
DepthKnown_A	472825360	472689929	0	0
RvalidKnown_A	472825360	472689929	0	0
WreadyKnown_A	472825360	472689929	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	435866	0	0
T2	2099	100	0	0
T3	1462	0	0	0
T4	2459	0	0	0
T5	13662	0	0	0
T6	11901	56	0	0
T7	130782	192	0	0
T8	33680	0	0	0
T9	26037	0	0	0
T10	358623	0	0	0
T11	25086	64	0	0
T25	0	1	0	0
T28	0	137	0	0
T29	0	2043	0	0
T39	0	427	0	0
T41	0	100	0	0
T42	0	147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	472825360	6480397	0	0
DepthKnown_A	472825360	472689929	0	0
RvalidKnown_A	472825360	472689929	0	0
WreadyKnown_A	472825360	472689929	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	6480397	0	0
T1	1357	67	0	0
T2	2099	1	0	0
T3	1462	1	0	0
T4	2459	26	0	0
T5	13662	86	0	0
T6	11901	533	0	0
T7	130782	2485	0	0
T8	33680	86	0	0
T9	26037	903	0	0
T10	358623	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	472825360	13907575	0	0
DepthKnown_A	472825360	472689929	0	0
RvalidKnown_A	472825360	472689929	0	0
WreadyKnown_A	472825360	472689929	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	13907575	0	0
T1	1357	67	0	0
T2	2099	1	0	0
T3	1462	1	0	0
T4	2459	26	0	0
T5	13662	270	0	0
T6	11901	1745	0	0
T7	130782	2456	0	0
T8	33680	259	0	0
T9	26037	3801	0	0
T10	358623	59	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472825360	472689929	0	0
T1	1357	1275	0	0
T2	2099	2017	0	0
T3	1462	1366	0	0
T4	2459	2397	0	0
T5	13662	13580	0	0
T6	11901	11805	0	0
T7	130782	130727	0	0
T8	33680	33586	0	0
T9	26037	25973	0	0
T10	358623	358537	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0