Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3482170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4113688

1

T1

1

T3

110

T4

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4133230	1			T1	43		T2	1		T3	101
values[0x0]	1730867	1			T3	52		T4	22		T5	68
values[0x1]	1731761	1			T3	48		T4	15		T5	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2465644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5130214

1

T1

14

T3

160

T4

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26553	1			T7	9		T16	1		T24	4
valid_sources[0x01]	25816	1			T7	2		T12	4		T27	5
valid_sources[0x02]	27458	1			T5	1		T6	1		T7	2
valid_sources[0x03]	28194	1			T6	1		T12	4		T18	3
valid_sources[0x04]	25955	1			T7	2		T12	8		T18	5
valid_sources[0x05]	29716	1			T5	1		T12	1		T14	1
valid_sources[0x06]	28243	1			T5	3		T7	4		T12	4
valid_sources[0x07]	27833	1			T7	5		T12	2		T39	1
valid_sources[0x08]	26478	1			T4	2		T5	2		T6	2
valid_sources[0x09]	28414	1			T6	1		T7	2		T12	2
valid_sources[0x0a]	32671	1			T7	7		T12	1		T18	4
valid_sources[0x0b]	30227	1			T7	5		T12	3		T24	1
valid_sources[0x0c]	31731	1			T7	1		T12	1		T14	3
valid_sources[0x0d]	27303	1			T7	1		T12	5		T24	1
valid_sources[0x0e]	26184	1			T5	2		T6	1		T7	1
valid_sources[0x0f]	26954	1			T6	3		T7	2		T12	3
valid_sources[0x10]	26208	1			T5	2		T6	1		T7	4
valid_sources[0x11]	26382	1			T6	2		T12	2		T24	2
valid_sources[0x12]	29769	1			T7	5		T18	6		T20	4
valid_sources[0x13]	27821	1			T7	5		T16	2		T24	1
valid_sources[0x14]	28921	1			T5	4		T6	1		T7	2
valid_sources[0x15]	29118	1			T5	2		T7	4		T12	3
valid_sources[0x16]	30959	1			T6	4		T7	4		T12	2
valid_sources[0x17]	25917	1			T10	3		T24	1		T26	2
valid_sources[0x18]	26607	1			T7	6		T12	6		T16	2
valid_sources[0x19]	30300	1			T7	3		T10	1		T12	3
valid_sources[0x1a]	30788	1			T7	1		T11	54		T12	4
valid_sources[0x1b]	24356	1			T5	1		T12	9		T18	3
valid_sources[0x1c]	35366	1			T6	1		T7	2		T11	2
valid_sources[0x1d]	27812	1			T5	1		T6	2		T7	1
valid_sources[0x1e]	30320	1			T1	7		T7	10		T12	4
valid_sources[0x1f]	29913	1			T5	2		T7	8		T12	4
valid_sources[0x20]	49089	1			T5	5		T7	2		T12	1
valid_sources[0x21]	28866	1			T4	1		T6	3		T7	2
valid_sources[0x22]	28252	1			T5	3		T7	2		T12	4
valid_sources[0x23]	30154	1			T12	4		T14	2		T24	3
valid_sources[0x24]	30467	1			T12	2		T14	1		T16	2
valid_sources[0x25]	28900	1			T4	1		T6	2		T7	4
valid_sources[0x26]	41180	1			T12	3		T18	5		T20	6
valid_sources[0x27]	30836	1			T7	6		T12	5		T18	4
valid_sources[0x28]	28312	1			T7	4		T12	4		T24	2
valid_sources[0x29]	30515	1			T6	1		T7	7		T12	7
valid_sources[0x2a]	29788	1			T6	1		T24	2		T18	7
valid_sources[0x2b]	29060	1			T6	3		T7	5		T12	1
valid_sources[0x2c]	28755	1			T3	6		T5	1		T6	2
valid_sources[0x2d]	27112	1			T3	6		T6	1		T7	9
valid_sources[0x2e]	29412	1			T16	1		T24	1		T26	2
valid_sources[0x2f]	27976	1			T6	2		T7	1		T12	12
valid_sources[0x30]	28210	1			T24	1		T18	4		T20	9
valid_sources[0x31]	32238	1			T6	2		T12	10		T24	1
valid_sources[0x32]	29963	1			T3	5		T7	2		T12	9
valid_sources[0x33]	31615	1			T7	2		T12	6		T13	497
valid_sources[0x34]	29453	1			T4	1		T6	1		T11	128
valid_sources[0x35]	29268	1			T6	1		T12	6		T26	9
valid_sources[0x36]	30317	1			T4	3		T7	7		T12	4
valid_sources[0x37]	27889	1			T5	4		T7	4		T12	2
valid_sources[0x38]	27283	1			T4	2		T7	3		T12	5
valid_sources[0x39]	26180	1			T10	52		T12	3		T14	1
valid_sources[0x3a]	27997	1			T3	8		T6	1		T7	4
valid_sources[0x3b]	32102	1			T3	2		T4	1		T7	1
valid_sources[0x3c]	24478	1			T6	1		T7	4		T12	2
valid_sources[0x3d]	26168	1			T7	7		T12	8		T16	1
valid_sources[0x3e]	28731	1			T6	4		T7	4		T18	4
valid_sources[0x3f]	25781	1			T7	4		T12	6		T24	3
valid_sources[0x40]	29258	1			T5	2		T6	1		T7	1
valid_sources[0x41]	27172	1			T3	1		T6	1		T7	13
valid_sources[0x42]	27315	1			T3	1		T6	1		T12	4
valid_sources[0x43]	27673	1			T6	1		T12	7		T14	1
valid_sources[0x44]	29891	1			T7	1		T12	2		T24	1
valid_sources[0x45]	27578	1			T7	8		T12	6		T18	3
valid_sources[0x46]	28821	1			T7	6		T12	4		T27	6
valid_sources[0x47]	30252	1			T6	1		T7	14		T11	341
valid_sources[0x48]	31620	1			T3	2		T6	1		T7	3
valid_sources[0x49]	29266	1			T6	1		T7	1		T26	1
valid_sources[0x4a]	62113	1			T3	2		T6	2		T7	3
valid_sources[0x4b]	27408	1			T6	1		T12	3		T18	6
valid_sources[0x4c]	28102	1			T6	1		T7	8		T12	4
valid_sources[0x4d]	28292	1			T6	1		T7	1		T12	2
valid_sources[0x4e]	30540	1			T6	1		T7	7		T12	1
valid_sources[0x4f]	28080	1			T6	1		T7	21		T12	3
valid_sources[0x50]	30156	1			T7	5		T12	1		T24	1
valid_sources[0x51]	25692	1			T6	2		T7	3		T12	4
valid_sources[0x52]	28730	1			T7	6		T12	6		T18	2
valid_sources[0x53]	28906	1			T6	2		T7	7		T12	2
valid_sources[0x54]	28328	1			T7	4		T12	1		T14	1
valid_sources[0x55]	26429	1			T7	3		T26	2		T18	3
valid_sources[0x56]	28533	1			T1	23		T5	1		T6	1
valid_sources[0x57]	30647	1			T7	8		T12	7		T39	1
valid_sources[0x58]	26158	1			T3	49		T7	1		T12	4
valid_sources[0x59]	30988	1			T7	3		T8	989		T12	3
valid_sources[0x5a]	29659	1			T3	3		T12	1		T16	2
valid_sources[0x5b]	28859	1			T12	3		T18	9		T19	96
valid_sources[0x5c]	53271	1			T7	4		T12	5		T14	2
valid_sources[0x5d]	25886	1			T6	3		T10	194		T12	7
valid_sources[0x5e]	49519	1			T7	5		T12	2		T14	2
valid_sources[0x5f]	27753	1			T9	398		T10	33		T12	3
valid_sources[0x60]	28602	1			T7	1		T12	2		T26	2
valid_sources[0x61]	25649	1			T7	4		T10	2		T12	2
valid_sources[0x62]	26956	1			T3	5		T5	2		T7	3
valid_sources[0x63]	29588	1			T7	4		T12	4		T26	7
valid_sources[0x64]	29043	1			T6	1		T12	3		T14	2
valid_sources[0x65]	33529	1			T6	1		T12	1		T27	1
valid_sources[0x66]	29732	1			T6	1		T7	8		T12	5
valid_sources[0x67]	27755	1			T7	1		T10	15		T12	2
valid_sources[0x68]	29165	1			T5	2		T7	5		T10	1
valid_sources[0x69]	30182	1			T3	4		T6	1		T7	1
valid_sources[0x6a]	28225	1			T7	4		T12	3		T26	1
valid_sources[0x6b]	29180	1			T4	3		T7	4		T12	3
valid_sources[0x6c]	27494	1			T6	3		T7	8		T12	4
valid_sources[0x6d]	29502	1			T3	1		T5	1		T7	2
valid_sources[0x6e]	29131	1			T7	2		T12	2		T14	2
valid_sources[0x6f]	27871	1			T7	2		T12	5		T14	1
valid_sources[0x70]	28430	1			T6	3		T7	7		T18	4
valid_sources[0x71]	25144	1			T3	5		T6	1		T7	3
valid_sources[0x72]	26418	1			T7	5		T12	7		T24	2
valid_sources[0x73]	27112	1			T7	4		T12	3		T27	2
valid_sources[0x74]	28039	1			T12	4		T14	1		T24	1
valid_sources[0x75]	28232	1			T5	1		T7	7		T12	6
valid_sources[0x76]	28579	1			T6	1		T7	4		T12	2
valid_sources[0x77]	30962	1			T5	1		T6	1		T7	1
valid_sources[0x78]	29551	1			T6	1		T9	449		T12	2
valid_sources[0x79]	31376	1			T6	1		T7	4		T12	2
valid_sources[0x7a]	35809	1			T6	1		T7	11		T10	62
valid_sources[0x7b]	26937	1			T2	1		T7	5		T12	2
valid_sources[0x7c]	29388	1			T4	2		T7	6		T12	2
valid_sources[0x7d]	28920	1			T12	3		T13	1		T14	1
valid_sources[0x7e]	34544	1			T6	1		T7	13		T11	1
valid_sources[0x7f]	30311	1			T5	2		T7	1		T12	2
valid_sources[0x80]	25872	1			T6	1		T7	9		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

977965

1

T1

1

T3

10

T6

21

values[0x0]

all_enables

biggest_size

1580089

1

T3

52

T4

20

T5

55

values[0x1]

all_enables

biggest_size

1555634

1

T3

48

T4

8

T5

53