Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3503744

1

T1

42

T2

1

T4

10

full_word

4112800

1

T1

1

T4

28

T5

108

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7616124	1			T1	43		T2	1		T4	38
auto[TlIntgErrCmd]	143	1			T146	2		T149	7		T151	7
auto[TlIntgErrData]	134	1			T146	3		T149	6		T151	6
auto[TlIntgErrBoth]	143	1			T146	5		T149	7		T151	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4135916

1

T1

43

T2

1

T4

1

auto[1]

3480628

1

T4

37

T5

132

T6

53

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3157607	1			T1	42		T2	1		T4	1
auto[TlIntgErrNone]	partial	auto[1]	345755	1			T4	9		T5	24		T6	23
auto[TlIntgErrNone]	full_word	auto[0]	978116	1			T1	1		T6	21		T7	5
auto[TlIntgErrNone]	full_word	auto[1]	3134646	1			T4	28		T5	108		T6	30
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T146	1		T149	1		T151	3
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T146	1		T149	6		T151	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T151	1		T350	1		T351	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T352	1		T353	1		T348	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T146	2		T149	2		T151	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T146	1		T149	2		T151	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T354	1		T355	1		T345	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T149	2		T151	1		T356	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T146	1		T149	2		T151	1
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T146	4		T149	4		T151	6
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T350	1		T355	1		T353	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T149	1		T354	2		T357	1