Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450850256	2812932	0	0
DepthKnown_A	450850256	450717354	0	0
RvalidKnown_A	450850256	450717354	0	0
WreadyKnown_A	450850256	450717354	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	2812932	0	0
T3	1515	100	0	0
T4	9503	0	0	0
T5	20309	0	0	0
T6	3588	0	0	0
T7	9732	1663	0	0
T8	7338	832	0	0
T9	14016	1663	0	0
T10	64780	0	0	0
T11	19700	2700	0	0
T12	220294	1663	0	0
T13	0	832	0	0
T17	0	832	0	0
T18	0	1663	0	0
T24	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450850256	3130195	0	0
DepthKnown_A	450850256	450717354	0	0
RvalidKnown_A	450850256	450717354	0	0
WreadyKnown_A	450850256	450717354	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	3130195	0	0
T3	1515	100	0	0
T4	9503	0	0	0
T5	20309	0	0	0
T6	3588	0	0	0
T7	9732	832	0	0
T8	7338	832	0	0
T9	14016	832	0	0
T10	64780	0	0	0
T11	19700	1361	0	0
T12	220294	832	0	0
T13	0	3820	0	0
T17	0	832	0	0
T18	0	832	0	0
T24	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450850256	190754	0	0
DepthKnown_A	450850256	450717354	0	0
RvalidKnown_A	450850256	450717354	0	0
WreadyKnown_A	450850256	450717354	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	190754	0	0
T3	1515	100	0	0
T4	9503	0	0	0
T5	20309	0	0	0
T6	3588	16	0	0
T7	9732	0	0	0
T8	7338	0	0	0
T9	14016	0	0	0
T10	64780	180	0	0
T11	19700	0	0	0
T12	220294	0	0	0
T24	0	100	0	0
T26	0	143	0	0
T29	0	14	0	0
T31	0	414	0	0
T43	0	100	0	0
T46	0	100	0	0
T47	0	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450850256	435622	0	0
DepthKnown_A	450850256	450717354	0	0
RvalidKnown_A	450850256	450717354	0	0
WreadyKnown_A	450850256	450717354	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	435622	0	0
T3	1515	100	0	0
T4	9503	0	0	0
T5	20309	0	0	0
T6	3588	87	0	0
T7	9732	0	0	0
T8	7338	0	0	0
T9	14016	0	0	0
T10	64780	832	0	0
T11	19700	0	0	0
T12	220294	0	0	0
T24	0	100	0	0
T26	0	660	0	0
T29	0	14	0	0
T31	0	414	0	0
T43	0	100	0	0
T46	0	100	0	0
T47	0	147	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450850256	6014313	0	0
DepthKnown_A	450850256	450717354	0	0
RvalidKnown_A	450850256	450717354	0	0
WreadyKnown_A	450850256	450717354	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	6014313	0	0
T1	1411	43	0	0
T2	1731	1	0	0
T3	1515	1	0	0
T4	9503	38	0	0
T5	20309	133	0	0
T6	3588	156	0	0
T7	9732	63	0	0
T8	7338	182	0	0
T9	14016	466	0	0
T10	64780	1733	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	450850256	13031908	0	0
DepthKnown_A	450850256	450717354	0	0
RvalidKnown_A	450850256	450717354	0	0
WreadyKnown_A	450850256	450717354	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	13031908	0	0
T1	1411	43	0	0
T2	1731	8	0	0
T3	1515	1	0	0
T4	9503	38	0	0
T5	20309	133	0	0
T6	3588	668	0	0
T7	9732	63	0	0
T8	7338	181	0	0
T9	14016	466	0	0
T10	64780	7434	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	450717354	0	0
T1	1411	1344	0	0
T2	1731	1667	0	0
T3	1515	1421	0	0
T4	9503	9418	0	0
T5	20309	20232	0	0
T6	3588	3536	0	0
T7	9732	9667	0	0
T8	7338	7284	0	0
T9	14016	13949	0	0
T10	64780	64689	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0