Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	450850256	3391	0	0
addr_swap_data_rd_A	450850256	1575	0	0
addr_swap_mask_rd_A	450850256	1459	0	0
cfg_rd_A	450850256	2080	0	0
cmd_filter_0_rd_A	450850256	10787	0	0
cmd_filter_1_rd_A	450850256	9587	0	0
cmd_filter_2_rd_A	450850256	10306	0	0
cmd_filter_3_rd_A	450850256	10273	0	0
cmd_filter_4_rd_A	450850256	9355	0	0
cmd_filter_5_rd_A	450850256	9460	0	0
cmd_filter_6_rd_A	450850256	9036	0	0
cmd_filter_7_rd_A	450850256	11806	0	0
cmd_info_0_rd_A	450850256	4181	0	0
cmd_info_10_rd_A	450850256	4483	0	0
cmd_info_11_rd_A	450850256	4574	0	0
cmd_info_12_rd_A	450850256	4723	0	0
cmd_info_13_rd_A	450850256	5781	0	0
cmd_info_14_rd_A	450850256	4978	0	0
cmd_info_15_rd_A	450850256	5305	0	0
cmd_info_16_rd_A	450850256	5327	0	0
cmd_info_17_rd_A	450850256	5288	0	0
cmd_info_18_rd_A	450850256	4703	0	0
cmd_info_19_rd_A	450850256	5365	0	0
cmd_info_1_rd_A	450850256	4929	0	0
cmd_info_20_rd_A	450850256	5257	0	0
cmd_info_21_rd_A	450850256	5104	0	0
cmd_info_22_rd_A	450850256	4893	0	0
cmd_info_23_rd_A	450850256	4501	0	0
cmd_info_2_rd_A	450850256	5382	0	0
cmd_info_3_rd_A	450850256	5156	0	0
cmd_info_4_rd_A	450850256	5307	0	0
cmd_info_5_rd_A	450850256	4762	0	0
cmd_info_6_rd_A	450850256	5016	0	0
cmd_info_7_rd_A	450850256	5003	0	0
cmd_info_8_rd_A	450850256	4987	0	0
cmd_info_9_rd_A	450850256	4986	0	0
cmd_info_en4b_rd_A	450850256	1896	0	0
cmd_info_ex4b_rd_A	450850256	1954	0	0
cmd_info_wrdi_rd_A	450850256	1936	0	0
cmd_info_wren_rd_A	450850256	1820	0	0
intercept_en_rd_A	450850256	2482	0	0
intr_enable_rd_A	450850256	4643	0	0
jedec_cc_rd_A	450850256	1827	0	0
jedec_id_rd_A	450850256	1784	0	0
mailbox_addr_rd_A	450850256	1565	0	0
payload_swap_data_rd_A	450850256	1725	0	0
payload_swap_mask_rd_A	450850256	1612	0	0
read_threshold_rd_A	450850256	1503	0	0
tpm_access_0_rd_A	450850256	2399	0	0
tpm_access_1_rd_A	450850256	1488	0	0
tpm_cfg_rd_A	450850256	2666	0	0
tpm_did_vid_rd_A	450850256	1917	0	0
tpm_int_enable_rd_A	450850256	1567	0	0
tpm_int_status_rd_A	450850256	1608	0	0
tpm_int_vector_rd_A	450850256	1580	0	0
tpm_intf_capability_rd_A	450850256	1657	0	0
tpm_rid_rd_A	450850256	1587	0	0
tpm_sts_rd_A	450850256	1631	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	3391	0	0
T145	6407	31	0	0
T146	9861	2	0	0
T147	8296	5	0	0
T148	12070	215	0	0
T150	22383	200	0	0
T152	2595	23	0	0
T153	8087	288	0	0
T161	4063	3	0	0
T162	12051	9	0	0
T163	15135	7	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1575	0	0
T131	2064	2	0	0
T163	15135	18	0	0
T173	3320	4	0	0
T189	19812	38	0	0
T196	91089	232	0	0
T197	18451	99	0	0
T198	11562	6	0	0
T199	14198	30	0	0
T200	5946	9	0	0
T201	14924	57	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1459	0	0
T131	2064	6	0	0
T163	15135	26	0	0
T173	3320	5	0	0
T189	19812	50	0	0
T196	91089	220	0	0
T197	18451	8	0	0
T198	11562	12	0	0
T199	14198	42	0	0
T200	5946	12	0	0
T201	14924	42	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	2080	0	0
T163	15135	61	0	0
T173	3320	4	0	0
T189	19812	23	0	0
T196	91089	251	0	0
T197	18451	55	0	0
T198	11562	9	0	0
T199	14198	39	0	0
T200	5946	2	0	0
T201	14924	54	0	0
T202	17854	34	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	10787	0	0
T163	15135	215	0	0
T173	3320	9	0	0
T189	19812	70	0	0
T196	91089	192	0	0
T197	18451	69	0	0
T198	11562	19	0	0
T199	14198	51	0	0
T200	5946	1	0	0
T201	14924	53	0	0
T202	17854	30	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	9587	0	0
T131	2064	8	0	0
T163	15135	158	0	0
T173	3320	6	0	0
T189	19812	55	0	0
T196	91089	232	0	0
T197	18451	32	0	0
T198	11562	133	0	0
T199	14198	47	0	0
T200	5946	8	0	0
T201	14924	47	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	10306	0	0
T163	15135	143	0	0
T189	19812	77	0	0
T196	91089	216	0	0
T197	18451	28	0	0
T198	11562	109	0	0
T199	14198	24	0	0
T200	5946	141	0	0
T201	14924	61	0	0
T202	17854	1	0	0
T203	8393	119	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	10273	0	0
T131	2064	1	0	0
T163	15135	123	0	0
T173	3320	6	0	0
T189	19812	82	0	0
T196	91089	220	0	0
T197	18451	92	0	0
T198	11562	379	0	0
T199	14198	31	0	0
T200	5946	98	0	0
T201	14924	60	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	9355	0	0
T131	2064	10	0	0
T156	15231	7	0	0
T163	15135	258	0	0
T173	3320	11	0	0
T189	19812	83	0	0
T196	91089	211	0	0
T197	18451	75	0	0
T198	11562	118	0	0
T199	14198	47	0	0
T200	5946	135	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	9460	0	0
T163	15135	246	0	0
T173	3320	5	0	0
T189	19812	54	0	0
T196	91089	203	0	0
T197	18451	58	0	0
T198	11562	144	0	0
T199	14198	17	0	0
T200	5946	142	0	0
T201	14924	56	0	0
T202	17854	32	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	9036	0	0
T131	2064	5	0	0
T163	15135	114	0	0
T173	3320	14	0	0
T189	19812	75	0	0
T196	91089	257	0	0
T197	18451	81	0	0
T198	11562	294	0	0
T199	14198	18	0	0
T200	5946	129	0	0
T201	14924	12	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	11806	0	0
T131	2064	5	0	0
T163	15135	328	0	0
T173	3320	11	0	0
T189	19812	95	0	0
T196	91089	201	0	0
T197	18451	103	0	0
T198	11562	136	0	0
T199	14198	79	0	0
T200	5946	15	0	0
T201	14924	28	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4181	0	0
T131	2064	5	0	0
T163	15135	25	0	0
T173	3320	7	0	0
T189	19812	55	0	0
T196	91089	216	0	0
T197	18451	42	0	0
T198	11562	12	0	0
T199	14198	16	0	0
T200	5946	43	0	0
T201	14924	36	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4483	0	0
T131	2064	3	0	0
T163	15135	31	0	0
T173	3320	1	0	0
T189	19812	52	0	0
T196	91089	224	0	0
T197	18451	62	0	0
T198	11562	13	0	0
T199	14198	79	0	0
T200	5946	10	0	0
T201	14924	29	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4574	0	0
T163	15135	66	0	0
T173	3320	11	0	0
T189	19812	62	0	0
T196	91089	184	0	0
T197	18451	35	0	0
T198	11562	146	0	0
T199	14198	56	0	0
T200	5946	9	0	0
T201	14924	69	0	0
T202	17854	42	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4723	0	0
T150	22383	1	0	0
T163	15135	78	0	0
T173	3320	9	0	0
T189	19812	45	0	0
T196	91089	237	0	0
T197	18451	95	0	0
T198	11562	103	0	0
T199	14198	56	0	0
T200	5946	9	0	0
T201	14924	70	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5781	0	0
T131	2064	3	0	0
T156	15231	6	0	0
T163	15135	69	0	0
T173	3320	11	0	0
T189	19812	51	0	0
T196	91089	231	0	0
T197	18451	32	0	0
T198	11562	115	0	0
T199	14198	43	0	0
T200	5946	15	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4978	0	0
T163	15135	108	0	0
T173	3320	6	0	0
T189	19812	56	0	0
T196	91089	216	0	0
T197	18451	128	0	0
T198	11562	41	0	0
T199	14198	43	0	0
T200	5946	14	0	0
T201	14924	65	0	0
T202	17854	77	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5305	0	0
T163	15135	123	0	0
T173	3320	14	0	0
T189	19812	31	0	0
T196	91089	243	0	0
T197	18451	77	0	0
T198	11562	159	0	0
T199	14198	27	0	0
T200	5946	14	0	0
T201	14924	42	0	0
T202	17854	28	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5327	0	0
T131	2064	4	0	0
T163	15135	102	0	0
T173	3320	12	0	0
T189	19812	54	0	0
T196	91089	238	0	0
T197	18451	82	0	0
T198	11562	80	0	0
T199	14198	39	0	0
T200	5946	64	0	0
T201	14924	72	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5288	0	0
T131	2064	3	0	0
T156	15231	4	0	0
T163	15135	72	0	0
T173	3320	6	0	0
T189	19812	55	0	0
T196	91089	240	0	0
T197	18451	106	0	0
T198	11562	80	0	0
T199	14198	26	0	0
T200	5946	13	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4703	0	0
T131	2064	8	0	0
T163	15135	123	0	0
T173	3320	15	0	0
T189	19812	57	0	0
T196	91089	218	0	0
T197	18451	39	0	0
T198	11562	110	0	0
T199	14198	37	0	0
T200	5946	12	0	0
T201	14924	9	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5365	0	0
T131	2064	5	0	0
T163	15135	22	0	0
T189	19812	33	0	0
T196	91089	223	0	0
T197	18451	52	0	0
T198	11562	62	0	0
T199	14198	28	0	0
T200	5946	50	0	0
T201	14924	15	0	0
T202	17854	20	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4929	0	0
T131	2064	4	0	0
T163	15135	111	0	0
T173	3320	1	0	0
T189	19812	45	0	0
T196	91089	211	0	0
T197	18451	64	0	0
T198	11562	152	0	0
T199	14198	15	0	0
T200	5946	6	0	0
T201	14924	40	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5257	0	0
T131	2064	3	0	0
T150	22383	2	0	0
T163	15135	109	0	0
T173	3320	4	0	0
T189	19812	38	0	0
T196	91089	204	0	0
T197	18451	95	0	0
T198	11562	105	0	0
T199	14198	72	0	0
T200	5946	13	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5104	0	0
T131	2064	9	0	0
T150	22383	9	0	0
T163	15135	201	0	0
T189	19812	34	0	0
T196	91089	242	0	0
T197	18451	63	0	0
T198	11562	47	0	0
T199	14198	46	0	0
T200	5946	4	0	0
T201	14924	30	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4893	0	0
T131	2064	7	0	0
T163	15135	139	0	0
T173	3320	5	0	0
T189	19812	68	0	0
T196	91089	221	0	0
T197	18451	82	0	0
T198	11562	86	0	0
T199	14198	12	0	0
T200	5946	64	0	0
T201	14924	49	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4501	0	0
T163	15135	66	0	0
T173	3320	13	0	0
T189	19812	72	0	0
T196	91089	239	0	0
T197	18451	65	0	0
T198	11562	94	0	0
T199	14198	49	0	0
T200	5946	49	0	0
T201	14924	21	0	0
T202	17854	24	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5382	0	0
T131	2064	6	0	0
T163	15135	180	0	0
T173	3320	5	0	0
T189	19812	31	0	0
T196	91089	229	0	0
T197	18451	44	0	0
T198	11562	54	0	0
T199	14198	81	0	0
T200	5946	49	0	0
T201	14924	46	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5156	0	0
T131	2064	7	0	0
T163	15135	136	0	0
T173	3320	5	0	0
T189	19812	84	0	0
T196	91089	224	0	0
T197	18451	59	0	0
T198	11562	62	0	0
T199	14198	87	0	0
T200	5946	12	0	0
T201	14924	10	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5307	0	0
T131	2064	7	0	0
T163	15135	79	0	0
T173	3320	4	0	0
T189	19812	54	0	0
T196	91089	291	0	0
T197	18451	85	0	0
T198	11562	67	0	0
T199	14198	55	0	0
T200	5946	10	0	0
T201	14924	83	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4762	0	0
T131	2064	3	0	0
T163	15135	33	0	0
T173	3320	7	0	0
T189	19812	76	0	0
T196	91089	203	0	0
T197	18451	39	0	0
T198	11562	80	0	0
T199	14198	19	0	0
T200	5946	72	0	0
T201	14924	27	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5016	0	0
T131	2064	7	0	0
T163	15135	153	0	0
T173	3320	8	0	0
T189	19812	53	0	0
T196	91089	229	0	0
T197	18451	52	0	0
T198	11562	64	0	0
T199	14198	21	0	0
T200	5946	68	0	0
T201	14924	31	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	5003	0	0
T163	15135	154	0	0
T173	3320	6	0	0
T189	19812	34	0	0
T196	91089	242	0	0
T197	18451	32	0	0
T198	11562	73	0	0
T199	14198	19	0	0
T200	5946	10	0	0
T201	14924	20	0	0
T202	17854	33	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4987	0	0
T131	2064	1	0	0
T163	15135	113	0	0
T173	3320	13	0	0
T189	19812	36	0	0
T196	91089	245	0	0
T197	18451	83	0	0
T198	11562	95	0	0
T199	14198	69	0	0
T200	5946	2	0	0
T201	14924	54	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4986	0	0
T163	15135	25	0	0
T173	3320	4	0	0
T189	19812	59	0	0
T196	91089	235	0	0
T197	18451	89	0	0
T198	11562	181	0	0
T199	14198	72	0	0
T200	5946	50	0	0
T201	14924	57	0	0
T202	17854	7	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1896	0	0
T131	2064	2	0	0
T163	15135	33	0	0
T173	3320	8	0	0
T189	19812	26	0	0
T196	91089	222	0	0
T197	18451	66	0	0
T198	11562	11	0	0
T199	14198	65	0	0
T200	5946	15	0	0
T201	14924	23	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1954	0	0
T163	15135	38	0	0
T173	3320	6	0	0
T189	19812	96	0	0
T196	91089	221	0	0
T197	18451	70	0	0
T198	11562	4	0	0
T199	14198	42	0	0
T200	5946	5	0	0
T201	14924	29	0	0
T202	17854	18	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1936	0	0
T131	2064	2	0	0
T163	15135	34	0	0
T173	3320	3	0	0
T189	19812	70	0	0
T196	91089	199	0	0
T197	18451	68	0	0
T198	11562	18	0	0
T199	14198	54	0	0
T200	5946	5	0	0
T201	14924	31	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1820	0	0
T131	2064	6	0	0
T163	15135	38	0	0
T173	3320	10	0	0
T189	19812	68	0	0
T196	91089	260	0	0
T197	18451	55	0	0
T198	11562	22	0	0
T199	14198	19	0	0
T200	5946	1	0	0
T201	14924	37	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	2482	0	0
T131	2064	3	0	0
T163	15135	44	0	0
T173	3320	1	0	0
T189	19812	24	0	0
T196	91089	226	0	0
T197	18451	20	0	0
T198	11562	17	0	0
T199	14198	39	0	0
T200	5946	17	0	0
T201	14924	69	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	4643	0	0
T21	4697	16	0	0
T22	5523	0	0	0
T28	429555	0	0	0
T32	1417	0	0	0
T36	0	5	0	0
T43	953	0	0	0
T49	48624	0	0	0
T51	0	41	0	0
T68	2931	0	0	0
T77	0	63	0	0
T121	745	0	0	0
T154	1706	0	0	0
T164	2894	0	0	0
T204	0	37	0	0
T205	0	24	0	0
T206	0	16	0	0
T207	0	66	0	0
T208	0	40	0	0
T209	0	9	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1827	0	0
T131	2064	3	0	0
T163	15135	19	0	0
T173	3320	8	0	0
T189	19812	57	0	0
T196	91089	223	0	0
T197	18451	54	0	0
T198	11562	22	0	0
T199	14198	28	0	0
T200	5946	13	0	0
T201	14924	44	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1784	0	0
T131	2064	2	0	0
T163	15135	32	0	0
T173	3320	7	0	0
T189	19812	42	0	0
T196	91089	215	0	0
T197	18451	21	0	0
T198	11562	25	0	0
T199	14198	39	0	0
T200	5946	20	0	0
T201	14924	31	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1565	0	0
T131	2064	1	0	0
T163	15135	32	0	0
T189	19812	58	0	0
T196	91089	197	0	0
T197	18451	65	0	0
T198	11562	11	0	0
T199	14198	50	0	0
T200	5946	13	0	0
T201	14924	2	0	0
T202	17854	47	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1725	0	0
T131	2064	1	0	0
T163	15135	18	0	0
T173	3320	6	0	0
T189	19812	98	0	0
T196	91089	219	0	0
T197	18451	32	0	0
T198	11562	11	0	0
T199	14198	67	0	0
T200	5946	5	0	0
T201	14924	79	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1612	0	0
T163	15135	12	0	0
T173	3320	5	0	0
T189	19812	54	0	0
T196	91089	253	0	0
T197	18451	41	0	0
T198	11562	9	0	0
T199	14198	17	0	0
T200	5946	12	0	0
T201	14924	16	0	0
T202	17854	55	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1503	0	0
T131	2064	7	0	0
T163	15135	30	0	0
T173	3320	6	0	0
T189	19812	66	0	0
T196	91089	248	0	0
T197	18451	35	0	0
T198	11562	8	0	0
T199	14198	23	0	0
T200	5946	9	0	0
T201	14924	22	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	2399	0	0
T131	2064	2	0	0
T163	15135	39	0	0
T173	3320	10	0	0
T189	19812	106	0	0
T196	91089	250	0	0
T197	18451	99	0	0
T198	11562	29	0	0
T199	14198	69	0	0
T200	5946	12	0	0
T201	14924	46	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1488	0	0
T163	15135	19	0	0
T173	3320	9	0	0
T189	19812	43	0	0
T196	91089	197	0	0
T197	18451	56	0	0
T198	11562	17	0	0
T199	14198	38	0	0
T200	5946	13	0	0
T201	14924	14	0	0
T202	17854	18	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	2666	0	0
T131	2064	1	0	0
T150	22383	8	0	0
T163	15135	67	0	0
T173	3320	5	0	0
T189	19812	50	0	0
T196	91089	202	0	0
T197	18451	76	0	0
T198	11562	33	0	0
T199	14198	46	0	0
T200	5946	13	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1917	0	0
T131	2064	1	0	0
T163	15135	35	0	0
T173	3320	4	0	0
T189	19812	48	0	0
T196	91089	251	0	0
T197	18451	105	0	0
T198	11562	15	0	0
T199	14198	39	0	0
T200	5946	13	0	0
T201	14924	36	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1567	0	0
T131	2064	1	0	0
T163	15135	27	0	0
T173	3320	13	0	0
T189	19812	58	0	0
T196	91089	237	0	0
T197	18451	46	0	0
T198	11562	21	0	0
T199	14198	40	0	0
T200	5946	12	0	0
T201	14924	11	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1608	0	0
T131	2064	6	0	0
T163	15135	18	0	0
T173	3320	9	0	0
T189	19812	49	0	0
T196	91089	219	0	0
T197	18451	45	0	0
T198	11562	12	0	0
T199	14198	44	0	0
T200	5946	14	0	0
T201	14924	73	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1580	0	0
T131	2064	2	0	0
T163	15135	23	0	0
T173	3320	6	0	0
T189	19812	102	0	0
T196	91089	193	0	0
T197	18451	67	0	0
T198	11562	9	0	0
T199	14198	44	0	0
T200	5946	6	0	0
T201	14924	34	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1657	0	0
T163	15135	17	0	0
T173	3320	7	0	0
T189	19812	79	0	0
T196	91089	259	0	0
T197	18451	85	0	0
T198	11562	13	0	0
T199	14198	35	0	0
T200	5946	3	0	0
T201	14924	38	0	0
T202	17854	69	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1587	0	0
T131	2064	5	0	0
T163	15135	10	0	0
T173	3320	3	0	0
T189	19812	48	0	0
T196	91089	200	0	0
T197	18451	38	0	0
T198	11562	10	0	0
T199	14198	44	0	0
T200	5946	5	0	0
T201	14924	60	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	450850256	1631	0	0
T163	15135	19	0	0
T173	3320	7	0	0
T189	19812	52	0	0
T196	91089	198	0	0
T197	18451	105	0	0
T198	11562	11	0	0
T199	14198	40	0	0
T200	5946	5	0	0
T201	14924	33	0	0
T202	17854	33	0	0