Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3557291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4443458

1

T1

1

T2

8

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4449861	1			T1	75		T2	1		T3	1
values[0x0]	1773583	1			T2	5		T4	3		T5	53
values[0x1]	1777305	1			T2	4		T4	1		T5	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2543924	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5456825

1

T1

27

T2

9

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31297	1			T7	3		T9	7		T28	1
valid_sources[0x01]	30529	1			T7	6		T9	8		T28	2
valid_sources[0x02]	32106	1			T7	3		T9	1		T28	1
valid_sources[0x03]	31849	1			T7	1		T8	1		T28	1
valid_sources[0x04]	29365	1			T7	2		T9	3		T28	1
valid_sources[0x05]	29921	1			T7	2		T9	3		T12	4
valid_sources[0x06]	28152	1			T7	4		T9	3		T12	7
valid_sources[0x07]	29878	1			T7	1		T9	2		T28	1
valid_sources[0x08]	28991	1			T7	2		T9	3		T12	4
valid_sources[0x09]	29073	1			T7	2		T9	4		T10	1
valid_sources[0x0a]	30147	1			T7	6		T12	2		T13	4
valid_sources[0x0b]	30705	1			T7	7		T9	5		T12	3
valid_sources[0x0c]	32461	1			T7	4		T9	8		T28	1
valid_sources[0x0d]	32647	1			T7	1		T9	2		T11	8
valid_sources[0x0e]	31055	1			T7	4		T9	7		T28	1
valid_sources[0x0f]	31539	1			T7	4		T9	5		T12	3
valid_sources[0x10]	31778	1			T7	7		T8	1		T9	8
valid_sources[0x11]	27860	1			T7	6		T9	3		T28	3
valid_sources[0x12]	27553	1			T7	3		T9	2		T12	3
valid_sources[0x13]	29078	1			T7	3		T28	2		T12	4
valid_sources[0x14]	37003	1			T7	5		T9	1		T13	9
valid_sources[0x15]	31780	1			T7	5		T8	3		T9	1
valid_sources[0x16]	28996	1			T7	4		T9	1		T12	7
valid_sources[0x17]	28283	1			T7	1		T9	6		T12	4
valid_sources[0x18]	29984	1			T7	3		T28	2		T12	3
valid_sources[0x19]	30111	1			T7	4		T9	2		T12	1
valid_sources[0x1a]	34123	1			T7	1		T9	2		T11	9
valid_sources[0x1b]	29205	1			T1	4		T7	2		T9	6
valid_sources[0x1c]	34154	1			T7	5		T9	4		T28	1
valid_sources[0x1d]	29845	1			T7	2		T9	8		T28	1
valid_sources[0x1e]	31290	1			T7	3		T9	1		T28	1
valid_sources[0x1f]	29901	1			T7	5		T9	4		T12	1
valid_sources[0x20]	28043	1			T1	2		T7	7		T9	5
valid_sources[0x21]	29358	1			T1	1		T7	5		T9	4
valid_sources[0x22]	31642	1			T5	201		T7	3		T9	3
valid_sources[0x23]	28703	1			T7	1		T9	6		T28	2
valid_sources[0x24]	34162	1			T7	1		T9	7		T28	1
valid_sources[0x25]	30914	1			T7	1		T9	2		T28	1
valid_sources[0x26]	30529	1			T7	4		T9	4		T28	1
valid_sources[0x27]	27581	1			T7	2		T9	6		T28	1
valid_sources[0x28]	29889	1			T7	3		T9	2		T12	7
valid_sources[0x29]	29757	1			T7	1		T9	7		T12	1
valid_sources[0x2a]	33744	1			T7	3		T9	11		T12	4
valid_sources[0x2b]	31635	1			T1	1		T7	5		T12	11
valid_sources[0x2c]	27716	1			T7	7		T9	7		T12	5
valid_sources[0x2d]	37890	1			T7	4		T28	2		T12	8
valid_sources[0x2e]	28985	1			T7	2		T8	1		T9	2
valid_sources[0x2f]	29006	1			T7	3		T9	3		T28	1
valid_sources[0x30]	27221	1			T7	2		T9	1		T28	1
valid_sources[0x31]	27983	1			T1	1		T7	1		T9	3
valid_sources[0x32]	34487	1			T7	4		T9	3		T12	10
valid_sources[0x33]	29766	1			T7	5		T9	3		T28	2
valid_sources[0x34]	32155	1			T1	1		T7	1		T9	4
valid_sources[0x35]	30328	1			T6	280		T7	4		T9	1
valid_sources[0x36]	28486	1			T7	3		T11	2		T12	2
valid_sources[0x37]	37311	1			T7	5		T9	1		T28	2
valid_sources[0x38]	32450	1			T7	3		T8	2		T9	10
valid_sources[0x39]	32139	1			T7	1		T9	9		T28	3
valid_sources[0x3a]	29018	1			T9	3		T28	1		T12	7
valid_sources[0x3b]	34489	1			T7	4		T9	2		T28	1
valid_sources[0x3c]	29628	1			T7	4		T12	6		T13	11
valid_sources[0x3d]	29584	1			T3	1		T7	3		T9	5
valid_sources[0x3e]	28506	1			T7	3		T9	1		T28	2
valid_sources[0x3f]	29633	1			T7	1		T9	9		T12	6
valid_sources[0x40]	29946	1			T7	3		T9	4		T12	5
valid_sources[0x41]	27624	1			T7	3		T9	4		T12	7
valid_sources[0x42]	31500	1			T7	6		T9	3		T12	8
valid_sources[0x43]	31230	1			T7	2		T9	4		T12	2
valid_sources[0x44]	35250	1			T1	1		T7	2		T28	1
valid_sources[0x45]	28163	1			T7	6		T28	1		T12	3
valid_sources[0x46]	34207	1			T7	2		T9	2		T12	5
valid_sources[0x47]	28879	1			T7	4		T12	1		T13	9
valid_sources[0x48]	28215	1			T7	3		T9	6		T12	6
valid_sources[0x49]	30159	1			T7	2		T9	5		T12	5
valid_sources[0x4a]	31121	1			T7	2		T9	1		T12	8
valid_sources[0x4b]	33611	1			T7	6		T9	5		T28	1
valid_sources[0x4c]	28976	1			T7	1		T9	2		T28	4
valid_sources[0x4d]	39000	1			T7	5		T9	9		T28	1
valid_sources[0x4e]	30015	1			T7	4		T8	1		T9	3
valid_sources[0x4f]	31471	1			T7	3		T9	6		T11	7
valid_sources[0x50]	35894	1			T12	5		T13	13		T14	3
valid_sources[0x51]	31840	1			T7	5		T9	4		T28	1
valid_sources[0x52]	29979	1			T7	3		T9	3		T12	2
valid_sources[0x53]	29329	1			T7	5		T9	5		T28	1
valid_sources[0x54]	28583	1			T7	12		T9	2		T12	3
valid_sources[0x55]	29374	1			T7	3		T9	4		T28	1
valid_sources[0x56]	32627	1			T7	1		T9	5		T12	3
valid_sources[0x57]	29986	1			T7	6		T9	1		T12	6
valid_sources[0x58]	30016	1			T9	5		T28	1		T12	6
valid_sources[0x59]	36056	1			T7	2		T12	9		T13	7
valid_sources[0x5a]	31127	1			T7	3		T9	2		T12	9
valid_sources[0x5b]	27099	1			T7	4		T9	1		T12	7
valid_sources[0x5c]	30650	1			T7	8		T9	2		T12	6
valid_sources[0x5d]	30170	1			T7	7		T9	5		T28	1
valid_sources[0x5e]	33661	1			T7	3		T9	2		T12	8
valid_sources[0x5f]	30199	1			T1	2		T7	2		T9	5
valid_sources[0x60]	31259	1			T12	5		T13	12		T20	6
valid_sources[0x61]	28855	1			T7	4		T9	7		T12	5
valid_sources[0x62]	29977	1			T7	3		T12	5		T13	14
valid_sources[0x63]	27890	1			T7	2		T28	1		T12	2
valid_sources[0x64]	35096	1			T7	1		T28	1		T12	5
valid_sources[0x65]	27868	1			T1	1		T28	1		T12	3
valid_sources[0x66]	29650	1			T1	7		T7	9		T9	11
valid_sources[0x67]	29688	1			T1	2		T7	6		T12	4
valid_sources[0x68]	33928	1			T7	4		T9	3		T27	1
valid_sources[0x69]	34556	1			T1	3		T7	4		T9	1
valid_sources[0x6a]	30575	1			T7	4		T9	5		T12	2
valid_sources[0x6b]	27487	1			T7	10		T9	6		T12	2
valid_sources[0x6c]	34272	1			T1	2		T7	3		T28	1
valid_sources[0x6d]	31153	1			T7	3		T12	1		T13	12
valid_sources[0x6e]	30625	1			T7	3		T9	6		T12	4
valid_sources[0x6f]	30188	1			T7	3		T9	5		T28	1
valid_sources[0x70]	26263	1			T7	3		T8	2		T9	2
valid_sources[0x71]	34450	1			T1	2		T7	6		T9	9
valid_sources[0x72]	29821	1			T7	3		T28	2		T12	10
valid_sources[0x73]	30574	1			T9	1		T12	11		T13	6
valid_sources[0x74]	30601	1			T7	9		T9	13		T28	1
valid_sources[0x75]	33681	1			T7	2		T9	3		T28	2
valid_sources[0x76]	30877	1			T7	2		T9	3		T28	1
valid_sources[0x77]	30130	1			T7	4		T9	4		T12	3
valid_sources[0x78]	27630	1			T7	8		T9	2		T28	2
valid_sources[0x79]	32215	1			T7	1		T9	3		T28	1
valid_sources[0x7a]	26493	1			T7	3		T9	5		T12	4
valid_sources[0x7b]	30822	1			T7	2		T9	8		T27	5
valid_sources[0x7c]	29473	1			T1	4		T7	8		T9	5
valid_sources[0x7d]	30211	1			T7	5		T9	3		T12	2
valid_sources[0x7e]	27442	1			T7	2		T9	4		T28	1
valid_sources[0x7f]	31303	1			T7	4		T9	3		T28	2
valid_sources[0x80]	31760	1			T7	4		T9	2		T12	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1208828

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1628249

1

T2

4

T4

2

T5

53

values[0x1]

all_enables

biggest_size

1606381

1

T2

3

T4

1

T5

47