Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3579017

1

T1

74

T2

2

T4

2

full_word

4442663

1

T1

1

T2

8

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8021310	1			T1	75		T2	10		T3	1
auto[TlIntgErrCmd]	133	1			T111	5		T114	5		T115	11
auto[TlIntgErrData]	118	1			T111	2		T114	10		T115	13
auto[TlIntgErrBoth]	119	1			T111	3		T114	5		T115	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4452456

1

T1

75

T2

1

T3

1

auto[1]

3569224

1

T2

9

T4

4

T6

50

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3243279	1			T1	74		T4	1		T6	213
auto[TlIntgErrNone]	partial	auto[1]	335397	1			T2	2		T4	1		T6	18
auto[TlIntgErrNone]	full_word	auto[0]	1209014	1			T1	1		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3233620	1			T2	7		T4	3		T6	32
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T111	2		T114	1		T115	4
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T111	2		T114	4		T115	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T111	1		T195	1		T196	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T115	1		T126	1		T189	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T111	2		T114	4		T115	6
auto[TlIntgErrData]	partial	auto[1]	49	1			T114	5		T115	6		T126	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T114	1		T190	1		T197	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T115	1		T194	1		T195	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T111	2		T114	2		T115	2
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T111	1		T114	3		T115	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T115	1		T126	1		T190	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T126	1		T191	1		T198	1