Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492849833	3022535	0	0
DepthKnown_A	492849833	492718323	0	0
RvalidKnown_A	492849833	492718323	0	0
WreadyKnown_A	492849833	492718323	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	3022535	0	0
T5	1202	100	0	0
T6	6825	0	0	0
T7	2668	1663	0	0
T8	1126	0	0	0
T9	18396	1663	0	0
T10	5781	0	0	0
T11	1446	0	0	0
T12	10058	1663	0	0
T13	0	832	0	0
T14	0	832	0	0
T17	0	1663	0	0
T18	0	1663	0	0
T19	0	832	0	0
T27	991	0	0	0
T28	1403	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492849833	3512809	0	0
DepthKnown_A	492849833	492718323	0	0
RvalidKnown_A	492849833	492718323	0	0
WreadyKnown_A	492849833	492718323	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	3512809	0	0
T5	1202	100	0	0
T6	6825	0	0	0
T7	2668	832	0	0
T8	1126	0	0	0
T9	18396	832	0	0
T10	5781	0	0	0
T11	1446	0	0	0
T12	10058	832	0	0
T13	0	832	0	0
T14	0	2608	0	0
T17	0	832	0	0
T18	0	832	0	0
T19	0	832	0	0
T27	991	0	0	0
T28	1403	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492849833	192861	0	0
DepthKnown_A	492849833	492718323	0	0
RvalidKnown_A	492849833	492718323	0	0
WreadyKnown_A	492849833	492718323	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	192861	0	0
T5	1202	100	0	0
T6	6825	11	0	0
T7	2668	0	0	0
T8	1126	0	0	0
T9	18396	0	0	0
T10	5781	0	0	0
T11	1446	0	0	0
T12	10058	0	0	0
T16	0	49	0	0
T27	991	0	0	0
T28	1403	100	0	0
T30	0	440	0	0
T31	0	23	0	0
T32	0	852	0	0
T34	0	870	0	0
T45	0	100	0	0
T46	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492849833	497267	0	0
DepthKnown_A	492849833	492718323	0	0
RvalidKnown_A	492849833	492718323	0	0
WreadyKnown_A	492849833	492718323	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	497267	0	0
T5	1202	100	0	0
T6	6825	49	0	0
T7	2668	0	0	0
T8	1126	0	0	0
T9	18396	0	0	0
T10	5781	0	0	0
T11	1446	0	0	0
T12	10058	0	0	0
T16	0	49	0	0
T27	991	0	0	0
T28	1403	100	0	0
T30	0	2134	0	0
T31	0	112	0	0
T32	0	2511	0	0
T34	0	870	0	0
T45	0	502	0	0
T46	0	310	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492849833	6274661	0	0
DepthKnown_A	492849833	492718323	0	0
RvalidKnown_A	492849833	492718323	0	0
WreadyKnown_A	492849833	492718323	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	6274661	0	0
T1	2114	75	0	0
T2	1227	10	0	0
T3	840	1	0	0
T4	1443	5	0	0
T5	1202	1	0	0
T6	6825	269	0	0
T7	2668	49	0	0
T8	1126	17	0	0
T9	18396	63	0	0
T10	5781	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	492849833	14482587	0	0
DepthKnown_A	492849833	492718323	0	0
RvalidKnown_A	492849833	492718323	0	0
WreadyKnown_A	492849833	492718323	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	14482587	0	0
T1	2114	349	0	0
T2	1227	42	0	0
T3	840	1	0	0
T4	1443	5	0	0
T5	1202	1	0	0
T6	6825	1180	0	0
T7	2668	49	0	0
T8	1126	50	0	0
T9	18396	63	0	0
T10	5781	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492849833	492718323	0	0
T1	2114	2064	0	0
T2	1227	1128	0	0
T3	840	787	0	0
T4	1443	1386	0	0
T5	1202	1131	0	0
T6	6825	6737	0	0
T7	2668	2580	0	0
T8	1126	1054	0	0
T9	18396	18318	0	0
T10	5781	4182	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0