Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
3415 | 
0 | 
0 | 
| T110 | 
5916 | 
194 | 
0 | 
0 | 
| T111 | 
9552 | 
1 | 
0 | 
0 | 
| T112 | 
8556 | 
4 | 
0 | 
0 | 
| T113 | 
7117 | 
318 | 
0 | 
0 | 
| T114 | 
19577 | 
3 | 
0 | 
0 | 
| T115 | 
81208 | 
7 | 
0 | 
0 | 
| T116 | 
2480 | 
8 | 
0 | 
0 | 
| T117 | 
17120 | 
226 | 
0 | 
0 | 
| T119 | 
15718 | 
204 | 
0 | 
0 | 
| T124 | 
11743 | 
2 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1760 | 
0 | 
0 | 
| T124 | 
11743 | 
18 | 
0 | 
0 | 
| T128 | 
11757 | 
9 | 
0 | 
0 | 
| T131 | 
4517 | 
7 | 
0 | 
0 | 
| T133 | 
4495 | 
3 | 
0 | 
0 | 
| T155 | 
6498 | 
11 | 
0 | 
0 | 
| T160 | 
123851 | 
761 | 
0 | 
0 | 
| T161 | 
20972 | 
30 | 
0 | 
0 | 
| T162 | 
39055 | 
267 | 
0 | 
0 | 
| T163 | 
12328 | 
16 | 
0 | 
0 | 
| T164 | 
14332 | 
15 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1878 | 
0 | 
0 | 
| T124 | 
11743 | 
11 | 
0 | 
0 | 
| T128 | 
11757 | 
20 | 
0 | 
0 | 
| T131 | 
4517 | 
1 | 
0 | 
0 | 
| T133 | 
4495 | 
6 | 
0 | 
0 | 
| T155 | 
6498 | 
5 | 
0 | 
0 | 
| T160 | 
123851 | 
843 | 
0 | 
0 | 
| T161 | 
20972 | 
44 | 
0 | 
0 | 
| T162 | 
39055 | 
235 | 
0 | 
0 | 
| T163 | 
12328 | 
47 | 
0 | 
0 | 
| T164 | 
14332 | 
3 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2520 | 
0 | 
0 | 
| T124 | 
11743 | 
19 | 
0 | 
0 | 
| T128 | 
11757 | 
29 | 
0 | 
0 | 
| T131 | 
4517 | 
15 | 
0 | 
0 | 
| T133 | 
4495 | 
14 | 
0 | 
0 | 
| T155 | 
6498 | 
17 | 
0 | 
0 | 
| T160 | 
123851 | 
746 | 
0 | 
0 | 
| T161 | 
20972 | 
29 | 
0 | 
0 | 
| T162 | 
39055 | 
316 | 
0 | 
0 | 
| T163 | 
12328 | 
33 | 
0 | 
0 | 
| T164 | 
14332 | 
17 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
11741 | 
0 | 
0 | 
| T124 | 
11743 | 
115 | 
0 | 
0 | 
| T128 | 
11757 | 
409 | 
0 | 
0 | 
| T131 | 
4517 | 
1 | 
0 | 
0 | 
| T133 | 
4495 | 
98 | 
0 | 
0 | 
| T155 | 
6498 | 
131 | 
0 | 
0 | 
| T160 | 
123851 | 
785 | 
0 | 
0 | 
| T161 | 
20972 | 
99 | 
0 | 
0 | 
| T162 | 
39055 | 
276 | 
0 | 
0 | 
| T163 | 
12328 | 
19 | 
0 | 
0 | 
| T164 | 
14332 | 
135 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
9101 | 
0 | 
0 | 
| T124 | 
11743 | 
152 | 
0 | 
0 | 
| T128 | 
11757 | 
142 | 
0 | 
0 | 
| T131 | 
4517 | 
13 | 
0 | 
0 | 
| T133 | 
4495 | 
102 | 
0 | 
0 | 
| T155 | 
6498 | 
86 | 
0 | 
0 | 
| T160 | 
123851 | 
771 | 
0 | 
0 | 
| T161 | 
20972 | 
79 | 
0 | 
0 | 
| T162 | 
39055 | 
295 | 
0 | 
0 | 
| T163 | 
12328 | 
26 | 
0 | 
0 | 
| T164 | 
14332 | 
164 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
9510 | 
0 | 
0 | 
| T124 | 
11743 | 
234 | 
0 | 
0 | 
| T128 | 
11757 | 
250 | 
0 | 
0 | 
| T131 | 
4517 | 
10 | 
0 | 
0 | 
| T133 | 
4495 | 
68 | 
0 | 
0 | 
| T155 | 
6498 | 
6 | 
0 | 
0 | 
| T160 | 
123851 | 
826 | 
0 | 
0 | 
| T161 | 
20972 | 
46 | 
0 | 
0 | 
| T162 | 
39055 | 
269 | 
0 | 
0 | 
| T163 | 
12328 | 
19 | 
0 | 
0 | 
| T164 | 
14332 | 
173 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
11147 | 
0 | 
0 | 
| T124 | 
11743 | 
108 | 
0 | 
0 | 
| T128 | 
11757 | 
347 | 
0 | 
0 | 
| T131 | 
4517 | 
2 | 
0 | 
0 | 
| T133 | 
4495 | 
110 | 
0 | 
0 | 
| T160 | 
123851 | 
772 | 
0 | 
0 | 
| T161 | 
20972 | 
79 | 
0 | 
0 | 
| T162 | 
39055 | 
312 | 
0 | 
0 | 
| T163 | 
12328 | 
13 | 
0 | 
0 | 
| T164 | 
14332 | 
125 | 
0 | 
0 | 
| T165 | 
4755 | 
3 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
10022 | 
0 | 
0 | 
| T124 | 
11743 | 
246 | 
0 | 
0 | 
| T128 | 
11757 | 
366 | 
0 | 
0 | 
| T131 | 
4517 | 
5 | 
0 | 
0 | 
| T133 | 
4495 | 
8 | 
0 | 
0 | 
| T155 | 
6498 | 
149 | 
0 | 
0 | 
| T160 | 
123851 | 
742 | 
0 | 
0 | 
| T161 | 
20972 | 
42 | 
0 | 
0 | 
| T162 | 
39055 | 
283 | 
0 | 
0 | 
| T163 | 
12328 | 
21 | 
0 | 
0 | 
| T164 | 
14332 | 
152 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
10210 | 
0 | 
0 | 
| T124 | 
11743 | 
166 | 
0 | 
0 | 
| T128 | 
11757 | 
149 | 
0 | 
0 | 
| T131 | 
4517 | 
3 | 
0 | 
0 | 
| T133 | 
4495 | 
89 | 
0 | 
0 | 
| T155 | 
6498 | 
80 | 
0 | 
0 | 
| T160 | 
123851 | 
745 | 
0 | 
0 | 
| T161 | 
20972 | 
63 | 
0 | 
0 | 
| T162 | 
39055 | 
314 | 
0 | 
0 | 
| T163 | 
12328 | 
23 | 
0 | 
0 | 
| T164 | 
14332 | 
73 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
10036 | 
0 | 
0 | 
| T124 | 
11743 | 
146 | 
0 | 
0 | 
| T128 | 
11757 | 
144 | 
0 | 
0 | 
| T131 | 
4517 | 
3 | 
0 | 
0 | 
| T133 | 
4495 | 
1 | 
0 | 
0 | 
| T160 | 
123851 | 
816 | 
0 | 
0 | 
| T161 | 
20972 | 
62 | 
0 | 
0 | 
| T162 | 
39055 | 
285 | 
0 | 
0 | 
| T163 | 
12328 | 
21 | 
0 | 
0 | 
| T164 | 
14332 | 
81 | 
0 | 
0 | 
| T165 | 
4755 | 
125 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
10393 | 
0 | 
0 | 
| T124 | 
11743 | 
210 | 
0 | 
0 | 
| T128 | 
11757 | 
136 | 
0 | 
0 | 
| T131 | 
4517 | 
8 | 
0 | 
0 | 
| T133 | 
4495 | 
97 | 
0 | 
0 | 
| T155 | 
6498 | 
162 | 
0 | 
0 | 
| T160 | 
123851 | 
774 | 
0 | 
0 | 
| T161 | 
20972 | 
69 | 
0 | 
0 | 
| T162 | 
39055 | 
249 | 
0 | 
0 | 
| T163 | 
12328 | 
31 | 
0 | 
0 | 
| T164 | 
14332 | 
6 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5019 | 
0 | 
0 | 
| T124 | 
11743 | 
19 | 
0 | 
0 | 
| T128 | 
11757 | 
75 | 
0 | 
0 | 
| T133 | 
4495 | 
49 | 
0 | 
0 | 
| T155 | 
6498 | 
32 | 
0 | 
0 | 
| T160 | 
123851 | 
744 | 
0 | 
0 | 
| T161 | 
20972 | 
83 | 
0 | 
0 | 
| T162 | 
39055 | 
265 | 
0 | 
0 | 
| T163 | 
12328 | 
28 | 
0 | 
0 | 
| T164 | 
14332 | 
54 | 
0 | 
0 | 
| T165 | 
4755 | 
1 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4935 | 
0 | 
0 | 
| T124 | 
11743 | 
59 | 
0 | 
0 | 
| T128 | 
11757 | 
180 | 
0 | 
0 | 
| T131 | 
4517 | 
4 | 
0 | 
0 | 
| T133 | 
4495 | 
8 | 
0 | 
0 | 
| T155 | 
6498 | 
41 | 
0 | 
0 | 
| T160 | 
123851 | 
757 | 
0 | 
0 | 
| T161 | 
20972 | 
56 | 
0 | 
0 | 
| T162 | 
39055 | 
287 | 
0 | 
0 | 
| T163 | 
12328 | 
17 | 
0 | 
0 | 
| T164 | 
14332 | 
56 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4146 | 
0 | 
0 | 
| T124 | 
11743 | 
106 | 
0 | 
0 | 
| T128 | 
11757 | 
92 | 
0 | 
0 | 
| T131 | 
4517 | 
10 | 
0 | 
0 | 
| T133 | 
4495 | 
25 | 
0 | 
0 | 
| T155 | 
6498 | 
5 | 
0 | 
0 | 
| T160 | 
123851 | 
780 | 
0 | 
0 | 
| T161 | 
20972 | 
44 | 
0 | 
0 | 
| T162 | 
39055 | 
262 | 
0 | 
0 | 
| T163 | 
12328 | 
16 | 
0 | 
0 | 
| T164 | 
14332 | 
42 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5049 | 
0 | 
0 | 
| T117 | 
17120 | 
5 | 
0 | 
0 | 
| T124 | 
11743 | 
39 | 
0 | 
0 | 
| T128 | 
11757 | 
61 | 
0 | 
0 | 
| T133 | 
4495 | 
54 | 
0 | 
0 | 
| T155 | 
6498 | 
3 | 
0 | 
0 | 
| T160 | 
123851 | 
762 | 
0 | 
0 | 
| T161 | 
20972 | 
119 | 
0 | 
0 | 
| T162 | 
39055 | 
296 | 
0 | 
0 | 
| T163 | 
12328 | 
9 | 
0 | 
0 | 
| T164 | 
14332 | 
49 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4640 | 
0 | 
0 | 
| T124 | 
11743 | 
55 | 
0 | 
0 | 
| T128 | 
11757 | 
7 | 
0 | 
0 | 
| T133 | 
4495 | 
7 | 
0 | 
0 | 
| T155 | 
6498 | 
14 | 
0 | 
0 | 
| T160 | 
123851 | 
746 | 
0 | 
0 | 
| T161 | 
20972 | 
75 | 
0 | 
0 | 
| T162 | 
39055 | 
256 | 
0 | 
0 | 
| T163 | 
12328 | 
31 | 
0 | 
0 | 
| T164 | 
14332 | 
16 | 
0 | 
0 | 
| T165 | 
4755 | 
53 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4780 | 
0 | 
0 | 
| T124 | 
11743 | 
37 | 
0 | 
0 | 
| T128 | 
11757 | 
145 | 
0 | 
0 | 
| T131 | 
4517 | 
6 | 
0 | 
0 | 
| T133 | 
4495 | 
45 | 
0 | 
0 | 
| T155 | 
6498 | 
7 | 
0 | 
0 | 
| T160 | 
123851 | 
867 | 
0 | 
0 | 
| T161 | 
20972 | 
55 | 
0 | 
0 | 
| T162 | 
39055 | 
292 | 
0 | 
0 | 
| T163 | 
12328 | 
16 | 
0 | 
0 | 
| T164 | 
14332 | 
12 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4668 | 
0 | 
0 | 
| T124 | 
11743 | 
59 | 
0 | 
0 | 
| T128 | 
11757 | 
148 | 
0 | 
0 | 
| T131 | 
4517 | 
11 | 
0 | 
0 | 
| T155 | 
6498 | 
68 | 
0 | 
0 | 
| T160 | 
123851 | 
754 | 
0 | 
0 | 
| T161 | 
20972 | 
15 | 
0 | 
0 | 
| T162 | 
39055 | 
236 | 
0 | 
0 | 
| T163 | 
12328 | 
38 | 
0 | 
0 | 
| T164 | 
14332 | 
35 | 
0 | 
0 | 
| T165 | 
4755 | 
6 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5183 | 
0 | 
0 | 
| T124 | 
11743 | 
61 | 
0 | 
0 | 
| T128 | 
11757 | 
116 | 
0 | 
0 | 
| T131 | 
4517 | 
19 | 
0 | 
0 | 
| T133 | 
4495 | 
38 | 
0 | 
0 | 
| T155 | 
6498 | 
59 | 
0 | 
0 | 
| T160 | 
123851 | 
787 | 
0 | 
0 | 
| T161 | 
20972 | 
37 | 
0 | 
0 | 
| T162 | 
39055 | 
266 | 
0 | 
0 | 
| T163 | 
12328 | 
56 | 
0 | 
0 | 
| T164 | 
14332 | 
51 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4949 | 
0 | 
0 | 
| T124 | 
11743 | 
75 | 
0 | 
0 | 
| T128 | 
11757 | 
17 | 
0 | 
0 | 
| T131 | 
4517 | 
3 | 
0 | 
0 | 
| T133 | 
4495 | 
2 | 
0 | 
0 | 
| T155 | 
6498 | 
10 | 
0 | 
0 | 
| T160 | 
123851 | 
823 | 
0 | 
0 | 
| T161 | 
20972 | 
76 | 
0 | 
0 | 
| T162 | 
39055 | 
234 | 
0 | 
0 | 
| T163 | 
12328 | 
16 | 
0 | 
0 | 
| T164 | 
14332 | 
101 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4907 | 
0 | 
0 | 
| T124 | 
11743 | 
14 | 
0 | 
0 | 
| T128 | 
11757 | 
158 | 
0 | 
0 | 
| T131 | 
4517 | 
5 | 
0 | 
0 | 
| T133 | 
4495 | 
71 | 
0 | 
0 | 
| T155 | 
6498 | 
29 | 
0 | 
0 | 
| T160 | 
123851 | 
799 | 
0 | 
0 | 
| T161 | 
20972 | 
69 | 
0 | 
0 | 
| T162 | 
39055 | 
244 | 
0 | 
0 | 
| T163 | 
12328 | 
34 | 
0 | 
0 | 
| T164 | 
14332 | 
56 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5040 | 
0 | 
0 | 
| T124 | 
11743 | 
50 | 
0 | 
0 | 
| T128 | 
11757 | 
107 | 
0 | 
0 | 
| T133 | 
4495 | 
10 | 
0 | 
0 | 
| T155 | 
6498 | 
33 | 
0 | 
0 | 
| T160 | 
123851 | 
767 | 
0 | 
0 | 
| T161 | 
20972 | 
53 | 
0 | 
0 | 
| T162 | 
39055 | 
265 | 
0 | 
0 | 
| T163 | 
12328 | 
14 | 
0 | 
0 | 
| T164 | 
14332 | 
31 | 
0 | 
0 | 
| T165 | 
4755 | 
42 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5388 | 
0 | 
0 | 
| T124 | 
11743 | 
108 | 
0 | 
0 | 
| T128 | 
11757 | 
113 | 
0 | 
0 | 
| T131 | 
4517 | 
4 | 
0 | 
0 | 
| T133 | 
4495 | 
49 | 
0 | 
0 | 
| T155 | 
6498 | 
36 | 
0 | 
0 | 
| T160 | 
123851 | 
782 | 
0 | 
0 | 
| T161 | 
20972 | 
93 | 
0 | 
0 | 
| T162 | 
39055 | 
278 | 
0 | 
0 | 
| T163 | 
12328 | 
5 | 
0 | 
0 | 
| T164 | 
14332 | 
58 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5268 | 
0 | 
0 | 
| T117 | 
17120 | 
7 | 
0 | 
0 | 
| T124 | 
11743 | 
68 | 
0 | 
0 | 
| T128 | 
11757 | 
15 | 
0 | 
0 | 
| T131 | 
4517 | 
4 | 
0 | 
0 | 
| T133 | 
4495 | 
1 | 
0 | 
0 | 
| T155 | 
6498 | 
1 | 
0 | 
0 | 
| T160 | 
123851 | 
765 | 
0 | 
0 | 
| T161 | 
20972 | 
44 | 
0 | 
0 | 
| T162 | 
39055 | 
288 | 
0 | 
0 | 
| T163 | 
12328 | 
39 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5569 | 
0 | 
0 | 
| T124 | 
11743 | 
56 | 
0 | 
0 | 
| T128 | 
11757 | 
110 | 
0 | 
0 | 
| T131 | 
4517 | 
7 | 
0 | 
0 | 
| T155 | 
6498 | 
43 | 
0 | 
0 | 
| T160 | 
123851 | 
867 | 
0 | 
0 | 
| T161 | 
20972 | 
70 | 
0 | 
0 | 
| T162 | 
39055 | 
295 | 
0 | 
0 | 
| T163 | 
12328 | 
28 | 
0 | 
0 | 
| T164 | 
14332 | 
62 | 
0 | 
0 | 
| T165 | 
4755 | 
71 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4917 | 
0 | 
0 | 
| T124 | 
11743 | 
57 | 
0 | 
0 | 
| T128 | 
11757 | 
170 | 
0 | 
0 | 
| T131 | 
4517 | 
17 | 
0 | 
0 | 
| T155 | 
6498 | 
14 | 
0 | 
0 | 
| T160 | 
123851 | 
780 | 
0 | 
0 | 
| T161 | 
20972 | 
77 | 
0 | 
0 | 
| T162 | 
39055 | 
264 | 
0 | 
0 | 
| T163 | 
12328 | 
44 | 
0 | 
0 | 
| T164 | 
14332 | 
33 | 
0 | 
0 | 
| T165 | 
4755 | 
3 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5256 | 
0 | 
0 | 
| T124 | 
11743 | 
54 | 
0 | 
0 | 
| T128 | 
11757 | 
52 | 
0 | 
0 | 
| T131 | 
4517 | 
22 | 
0 | 
0 | 
| T133 | 
4495 | 
34 | 
0 | 
0 | 
| T155 | 
6498 | 
44 | 
0 | 
0 | 
| T160 | 
123851 | 
795 | 
0 | 
0 | 
| T161 | 
20972 | 
89 | 
0 | 
0 | 
| T162 | 
39055 | 
309 | 
0 | 
0 | 
| T163 | 
12328 | 
32 | 
0 | 
0 | 
| T164 | 
14332 | 
30 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5395 | 
0 | 
0 | 
| T124 | 
11743 | 
74 | 
0 | 
0 | 
| T128 | 
11757 | 
101 | 
0 | 
0 | 
| T131 | 
4517 | 
22 | 
0 | 
0 | 
| T133 | 
4495 | 
52 | 
0 | 
0 | 
| T155 | 
6498 | 
61 | 
0 | 
0 | 
| T160 | 
123851 | 
824 | 
0 | 
0 | 
| T161 | 
20972 | 
66 | 
0 | 
0 | 
| T162 | 
39055 | 
276 | 
0 | 
0 | 
| T163 | 
12328 | 
4 | 
0 | 
0 | 
| T164 | 
14332 | 
53 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5249 | 
0 | 
0 | 
| T124 | 
11743 | 
58 | 
0 | 
0 | 
| T128 | 
11757 | 
126 | 
0 | 
0 | 
| T131 | 
4517 | 
5 | 
0 | 
0 | 
| T133 | 
4495 | 
71 | 
0 | 
0 | 
| T160 | 
123851 | 
767 | 
0 | 
0 | 
| T161 | 
20972 | 
54 | 
0 | 
0 | 
| T162 | 
39055 | 
286 | 
0 | 
0 | 
| T163 | 
12328 | 
7 | 
0 | 
0 | 
| T164 | 
14332 | 
58 | 
0 | 
0 | 
| T165 | 
4755 | 
5 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5217 | 
0 | 
0 | 
| T124 | 
11743 | 
11 | 
0 | 
0 | 
| T128 | 
11757 | 
47 | 
0 | 
0 | 
| T131 | 
4517 | 
4 | 
0 | 
0 | 
| T133 | 
4495 | 
35 | 
0 | 
0 | 
| T155 | 
6498 | 
63 | 
0 | 
0 | 
| T160 | 
123851 | 
794 | 
0 | 
0 | 
| T161 | 
20972 | 
61 | 
0 | 
0 | 
| T162 | 
39055 | 
256 | 
0 | 
0 | 
| T163 | 
12328 | 
13 | 
0 | 
0 | 
| T164 | 
14332 | 
9 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5318 | 
0 | 
0 | 
| T124 | 
11743 | 
52 | 
0 | 
0 | 
| T128 | 
11757 | 
79 | 
0 | 
0 | 
| T131 | 
4517 | 
8 | 
0 | 
0 | 
| T133 | 
4495 | 
2 | 
0 | 
0 | 
| T155 | 
6498 | 
3 | 
0 | 
0 | 
| T160 | 
123851 | 
807 | 
0 | 
0 | 
| T161 | 
20972 | 
56 | 
0 | 
0 | 
| T162 | 
39055 | 
241 | 
0 | 
0 | 
| T163 | 
12328 | 
36 | 
0 | 
0 | 
| T164 | 
14332 | 
54 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5138 | 
0 | 
0 | 
| T124 | 
11743 | 
59 | 
0 | 
0 | 
| T128 | 
11757 | 
99 | 
0 | 
0 | 
| T131 | 
4517 | 
5 | 
0 | 
0 | 
| T133 | 
4495 | 
3 | 
0 | 
0 | 
| T155 | 
6498 | 
1 | 
0 | 
0 | 
| T160 | 
123851 | 
847 | 
0 | 
0 | 
| T161 | 
20972 | 
56 | 
0 | 
0 | 
| T162 | 
39055 | 
274 | 
0 | 
0 | 
| T163 | 
12328 | 
22 | 
0 | 
0 | 
| T164 | 
14332 | 
69 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5030 | 
0 | 
0 | 
| T124 | 
11743 | 
109 | 
0 | 
0 | 
| T128 | 
11757 | 
19 | 
0 | 
0 | 
| T131 | 
4517 | 
2 | 
0 | 
0 | 
| T133 | 
4495 | 
23 | 
0 | 
0 | 
| T155 | 
6498 | 
7 | 
0 | 
0 | 
| T160 | 
123851 | 
700 | 
0 | 
0 | 
| T161 | 
20972 | 
58 | 
0 | 
0 | 
| T162 | 
39055 | 
177 | 
0 | 
0 | 
| T163 | 
12328 | 
48 | 
0 | 
0 | 
| T164 | 
14332 | 
31 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5043 | 
0 | 
0 | 
| T124 | 
11743 | 
41 | 
0 | 
0 | 
| T128 | 
11757 | 
8 | 
0 | 
0 | 
| T131 | 
4517 | 
8 | 
0 | 
0 | 
| T133 | 
4495 | 
42 | 
0 | 
0 | 
| T155 | 
6498 | 
9 | 
0 | 
0 | 
| T160 | 
123851 | 
803 | 
0 | 
0 | 
| T161 | 
20972 | 
61 | 
0 | 
0 | 
| T162 | 
39055 | 
256 | 
0 | 
0 | 
| T163 | 
12328 | 
32 | 
0 | 
0 | 
| T164 | 
14332 | 
34 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
5121 | 
0 | 
0 | 
| T124 | 
11743 | 
23 | 
0 | 
0 | 
| T128 | 
11757 | 
59 | 
0 | 
0 | 
| T131 | 
4517 | 
13 | 
0 | 
0 | 
| T155 | 
6498 | 
22 | 
0 | 
0 | 
| T160 | 
123851 | 
795 | 
0 | 
0 | 
| T161 | 
20972 | 
63 | 
0 | 
0 | 
| T162 | 
39055 | 
278 | 
0 | 
0 | 
| T163 | 
12328 | 
39 | 
0 | 
0 | 
| T164 | 
14332 | 
45 | 
0 | 
0 | 
| T166 | 
14367 | 
83 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2098 | 
0 | 
0 | 
| T124 | 
11743 | 
14 | 
0 | 
0 | 
| T128 | 
11757 | 
18 | 
0 | 
0 | 
| T131 | 
4517 | 
7 | 
0 | 
0 | 
| T133 | 
4495 | 
5 | 
0 | 
0 | 
| T155 | 
6498 | 
8 | 
0 | 
0 | 
| T160 | 
123851 | 
746 | 
0 | 
0 | 
| T161 | 
20972 | 
87 | 
0 | 
0 | 
| T162 | 
39055 | 
291 | 
0 | 
0 | 
| T163 | 
12328 | 
37 | 
0 | 
0 | 
| T164 | 
14332 | 
14 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2321 | 
0 | 
0 | 
| T124 | 
11743 | 
26 | 
0 | 
0 | 
| T128 | 
11757 | 
9 | 
0 | 
0 | 
| T131 | 
4517 | 
1 | 
0 | 
0 | 
| T133 | 
4495 | 
3 | 
0 | 
0 | 
| T155 | 
6498 | 
4 | 
0 | 
0 | 
| T160 | 
123851 | 
837 | 
0 | 
0 | 
| T161 | 
20972 | 
137 | 
0 | 
0 | 
| T162 | 
39055 | 
339 | 
0 | 
0 | 
| T163 | 
12328 | 
35 | 
0 | 
0 | 
| T164 | 
14332 | 
32 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2133 | 
0 | 
0 | 
| T124 | 
11743 | 
18 | 
0 | 
0 | 
| T128 | 
11757 | 
13 | 
0 | 
0 | 
| T131 | 
4517 | 
5 | 
0 | 
0 | 
| T155 | 
6498 | 
11 | 
0 | 
0 | 
| T160 | 
123851 | 
708 | 
0 | 
0 | 
| T161 | 
20972 | 
98 | 
0 | 
0 | 
| T162 | 
39055 | 
288 | 
0 | 
0 | 
| T163 | 
12328 | 
27 | 
0 | 
0 | 
| T164 | 
14332 | 
29 | 
0 | 
0 | 
| T165 | 
4755 | 
13 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2205 | 
0 | 
0 | 
| T124 | 
11743 | 
18 | 
0 | 
0 | 
| T128 | 
11757 | 
15 | 
0 | 
0 | 
| T131 | 
4517 | 
6 | 
0 | 
0 | 
| T133 | 
4495 | 
7 | 
0 | 
0 | 
| T155 | 
6498 | 
10 | 
0 | 
0 | 
| T160 | 
123851 | 
787 | 
0 | 
0 | 
| T161 | 
20972 | 
64 | 
0 | 
0 | 
| T162 | 
39055 | 
288 | 
0 | 
0 | 
| T163 | 
12328 | 
28 | 
0 | 
0 | 
| T164 | 
14332 | 
4 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2722 | 
0 | 
0 | 
| T124 | 
11743 | 
44 | 
0 | 
0 | 
| T128 | 
11757 | 
21 | 
0 | 
0 | 
| T131 | 
4517 | 
6 | 
0 | 
0 | 
| T133 | 
4495 | 
1 | 
0 | 
0 | 
| T155 | 
6498 | 
10 | 
0 | 
0 | 
| T160 | 
123851 | 
782 | 
0 | 
0 | 
| T161 | 
20972 | 
54 | 
0 | 
0 | 
| T162 | 
39055 | 
276 | 
0 | 
0 | 
| T163 | 
12328 | 
26 | 
0 | 
0 | 
| T164 | 
14332 | 
19 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
4436 | 
0 | 
0 | 
| T38 | 
492082 | 
41 | 
0 | 
0 | 
| T41 | 
0 | 
1 | 
0 | 
0 | 
| T43 | 
0 | 
32 | 
0 | 
0 | 
| T140 | 
114793 | 
0 | 
0 | 
0 | 
| T141 | 
1490 | 
0 | 
0 | 
0 | 
| T142 | 
164579 | 
0 | 
0 | 
0 | 
| T143 | 
2280 | 
0 | 
0 | 
0 | 
| T144 | 
100585 | 
0 | 
0 | 
0 | 
| T145 | 
1185 | 
0 | 
0 | 
0 | 
| T146 | 
761417 | 
0 | 
0 | 
0 | 
| T147 | 
7894 | 
0 | 
0 | 
0 | 
| T150 | 
0 | 
34 | 
0 | 
0 | 
| T167 | 
0 | 
35 | 
0 | 
0 | 
| T168 | 
0 | 
30 | 
0 | 
0 | 
| T169 | 
0 | 
13 | 
0 | 
0 | 
| T170 | 
0 | 
23 | 
0 | 
0 | 
| T171 | 
0 | 
14 | 
0 | 
0 | 
| T172 | 
0 | 
50 | 
0 | 
0 | 
| T173 | 
26971 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1990 | 
0 | 
0 | 
| T124 | 
11743 | 
21 | 
0 | 
0 | 
| T128 | 
11757 | 
14 | 
0 | 
0 | 
| T131 | 
4517 | 
2 | 
0 | 
0 | 
| T133 | 
4495 | 
2 | 
0 | 
0 | 
| T155 | 
6498 | 
13 | 
0 | 
0 | 
| T160 | 
123851 | 
757 | 
0 | 
0 | 
| T161 | 
20972 | 
53 | 
0 | 
0 | 
| T162 | 
39055 | 
232 | 
0 | 
0 | 
| T163 | 
12328 | 
22 | 
0 | 
0 | 
| T164 | 
14332 | 
16 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2056 | 
0 | 
0 | 
| T124 | 
11743 | 
8 | 
0 | 
0 | 
| T128 | 
11757 | 
20 | 
0 | 
0 | 
| T131 | 
4517 | 
7 | 
0 | 
0 | 
| T133 | 
4495 | 
7 | 
0 | 
0 | 
| T155 | 
6498 | 
5 | 
0 | 
0 | 
| T160 | 
123851 | 
806 | 
0 | 
0 | 
| T161 | 
20972 | 
46 | 
0 | 
0 | 
| T162 | 
39055 | 
243 | 
0 | 
0 | 
| T163 | 
12328 | 
15 | 
0 | 
0 | 
| T164 | 
14332 | 
5 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1860 | 
0 | 
0 | 
| T124 | 
11743 | 
17 | 
0 | 
0 | 
| T128 | 
11757 | 
16 | 
0 | 
0 | 
| T131 | 
4517 | 
7 | 
0 | 
0 | 
| T133 | 
4495 | 
4 | 
0 | 
0 | 
| T160 | 
123851 | 
800 | 
0 | 
0 | 
| T161 | 
20972 | 
32 | 
0 | 
0 | 
| T162 | 
39055 | 
286 | 
0 | 
0 | 
| T163 | 
12328 | 
9 | 
0 | 
0 | 
| T164 | 
14332 | 
23 | 
0 | 
0 | 
| T165 | 
4755 | 
1 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1877 | 
0 | 
0 | 
| T124 | 
11743 | 
14 | 
0 | 
0 | 
| T128 | 
11757 | 
20 | 
0 | 
0 | 
| T131 | 
4517 | 
5 | 
0 | 
0 | 
| T160 | 
123851 | 
798 | 
0 | 
0 | 
| T161 | 
20972 | 
63 | 
0 | 
0 | 
| T162 | 
39055 | 
266 | 
0 | 
0 | 
| T163 | 
12328 | 
63 | 
0 | 
0 | 
| T164 | 
14332 | 
21 | 
0 | 
0 | 
| T165 | 
4755 | 
8 | 
0 | 
0 | 
| T166 | 
14367 | 
30 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1889 | 
0 | 
0 | 
| T124 | 
11743 | 
15 | 
0 | 
0 | 
| T128 | 
11757 | 
24 | 
0 | 
0 | 
| T131 | 
4517 | 
4 | 
0 | 
0 | 
| T155 | 
6498 | 
8 | 
0 | 
0 | 
| T160 | 
123851 | 
832 | 
0 | 
0 | 
| T161 | 
20972 | 
80 | 
0 | 
0 | 
| T162 | 
39055 | 
243 | 
0 | 
0 | 
| T163 | 
12328 | 
26 | 
0 | 
0 | 
| T164 | 
14332 | 
5 | 
0 | 
0 | 
| T165 | 
4755 | 
7 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1956 | 
0 | 
0 | 
| T124 | 
11743 | 
18 | 
0 | 
0 | 
| T128 | 
11757 | 
14 | 
0 | 
0 | 
| T131 | 
4517 | 
3 | 
0 | 
0 | 
| T133 | 
4495 | 
6 | 
0 | 
0 | 
| T155 | 
6498 | 
1 | 
0 | 
0 | 
| T160 | 
123851 | 
769 | 
0 | 
0 | 
| T161 | 
20972 | 
133 | 
0 | 
0 | 
| T162 | 
39055 | 
274 | 
0 | 
0 | 
| T163 | 
12328 | 
25 | 
0 | 
0 | 
| T164 | 
14332 | 
5 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2747 | 
0 | 
0 | 
| T124 | 
11743 | 
20 | 
0 | 
0 | 
| T128 | 
11757 | 
22 | 
0 | 
0 | 
| T131 | 
4517 | 
12 | 
0 | 
0 | 
| T155 | 
6498 | 
28 | 
0 | 
0 | 
| T160 | 
123851 | 
814 | 
0 | 
0 | 
| T161 | 
20972 | 
47 | 
0 | 
0 | 
| T162 | 
39055 | 
295 | 
0 | 
0 | 
| T163 | 
12328 | 
9 | 
0 | 
0 | 
| T164 | 
14332 | 
34 | 
0 | 
0 | 
| T165 | 
4755 | 
9 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1832 | 
0 | 
0 | 
| T124 | 
11743 | 
10 | 
0 | 
0 | 
| T128 | 
11757 | 
6 | 
0 | 
0 | 
| T131 | 
4517 | 
2 | 
0 | 
0 | 
| T133 | 
4495 | 
4 | 
0 | 
0 | 
| T160 | 
123851 | 
735 | 
0 | 
0 | 
| T161 | 
20972 | 
70 | 
0 | 
0 | 
| T162 | 
39055 | 
276 | 
0 | 
0 | 
| T163 | 
12328 | 
23 | 
0 | 
0 | 
| T164 | 
14332 | 
8 | 
0 | 
0 | 
| T165 | 
4755 | 
9 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
3023 | 
0 | 
0 | 
| T124 | 
11743 | 
19 | 
0 | 
0 | 
| T128 | 
11757 | 
50 | 
0 | 
0 | 
| T131 | 
4517 | 
6 | 
0 | 
0 | 
| T133 | 
4495 | 
14 | 
0 | 
0 | 
| T155 | 
6498 | 
13 | 
0 | 
0 | 
| T160 | 
123851 | 
807 | 
0 | 
0 | 
| T161 | 
20972 | 
96 | 
0 | 
0 | 
| T162 | 
39055 | 
272 | 
0 | 
0 | 
| T163 | 
12328 | 
9 | 
0 | 
0 | 
| T164 | 
14332 | 
18 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2113 | 
0 | 
0 | 
| T124 | 
11743 | 
22 | 
0 | 
0 | 
| T128 | 
11757 | 
26 | 
0 | 
0 | 
| T133 | 
4495 | 
7 | 
0 | 
0 | 
| T155 | 
6498 | 
8 | 
0 | 
0 | 
| T160 | 
123851 | 
813 | 
0 | 
0 | 
| T161 | 
20972 | 
56 | 
0 | 
0 | 
| T162 | 
39055 | 
266 | 
0 | 
0 | 
| T163 | 
12328 | 
23 | 
0 | 
0 | 
| T164 | 
14332 | 
16 | 
0 | 
0 | 
| T165 | 
4755 | 
5 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1858 | 
0 | 
0 | 
| T124 | 
11743 | 
12 | 
0 | 
0 | 
| T128 | 
11757 | 
13 | 
0 | 
0 | 
| T131 | 
4517 | 
7 | 
0 | 
0 | 
| T155 | 
6498 | 
7 | 
0 | 
0 | 
| T160 | 
123851 | 
861 | 
0 | 
0 | 
| T161 | 
20972 | 
60 | 
0 | 
0 | 
| T162 | 
39055 | 
262 | 
0 | 
0 | 
| T163 | 
12328 | 
22 | 
0 | 
0 | 
| T164 | 
14332 | 
6 | 
0 | 
0 | 
| T166 | 
14367 | 
36 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1810 | 
0 | 
0 | 
| T124 | 
11743 | 
18 | 
0 | 
0 | 
| T128 | 
11757 | 
8 | 
0 | 
0 | 
| T131 | 
4517 | 
9 | 
0 | 
0 | 
| T133 | 
4495 | 
2 | 
0 | 
0 | 
| T160 | 
123851 | 
812 | 
0 | 
0 | 
| T161 | 
20972 | 
88 | 
0 | 
0 | 
| T162 | 
39055 | 
291 | 
0 | 
0 | 
| T163 | 
12328 | 
8 | 
0 | 
0 | 
| T164 | 
14332 | 
25 | 
0 | 
0 | 
| T166 | 
14367 | 
20 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1923 | 
0 | 
0 | 
| T124 | 
11743 | 
21 | 
0 | 
0 | 
| T128 | 
11757 | 
13 | 
0 | 
0 | 
| T131 | 
4517 | 
5 | 
0 | 
0 | 
| T133 | 
4495 | 
3 | 
0 | 
0 | 
| T155 | 
6498 | 
6 | 
0 | 
0 | 
| T160 | 
123851 | 
806 | 
0 | 
0 | 
| T161 | 
20972 | 
110 | 
0 | 
0 | 
| T162 | 
39055 | 
259 | 
0 | 
0 | 
| T163 | 
12328 | 
18 | 
0 | 
0 | 
| T164 | 
14332 | 
17 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1915 | 
0 | 
0 | 
| T124 | 
11743 | 
19 | 
0 | 
0 | 
| T128 | 
11757 | 
9 | 
0 | 
0 | 
| T131 | 
4517 | 
7 | 
0 | 
0 | 
| T133 | 
4495 | 
5 | 
0 | 
0 | 
| T155 | 
6498 | 
1 | 
0 | 
0 | 
| T160 | 
123851 | 
847 | 
0 | 
0 | 
| T161 | 
20972 | 
101 | 
0 | 
0 | 
| T162 | 
39055 | 
272 | 
0 | 
0 | 
| T163 | 
12328 | 
1 | 
0 | 
0 | 
| T164 | 
14332 | 
12 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
1789 | 
0 | 
0 | 
| T124 | 
11743 | 
17 | 
0 | 
0 | 
| T128 | 
11757 | 
8 | 
0 | 
0 | 
| T133 | 
4495 | 
3 | 
0 | 
0 | 
| T155 | 
6498 | 
3 | 
0 | 
0 | 
| T160 | 
123851 | 
735 | 
0 | 
0 | 
| T161 | 
20972 | 
121 | 
0 | 
0 | 
| T162 | 
39055 | 
284 | 
0 | 
0 | 
| T163 | 
12328 | 
22 | 
0 | 
0 | 
| T164 | 
14332 | 
11 | 
0 | 
0 | 
| T166 | 
14367 | 
16 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
492849833 | 
2026 | 
0 | 
0 | 
| T117 | 
17120 | 
4 | 
0 | 
0 | 
| T124 | 
11743 | 
18 | 
0 | 
0 | 
| T128 | 
11757 | 
10 | 
0 | 
0 | 
| T133 | 
4495 | 
8 | 
0 | 
0 | 
| T155 | 
6498 | 
8 | 
0 | 
0 | 
| T160 | 
123851 | 
830 | 
0 | 
0 | 
| T161 | 
20972 | 
103 | 
0 | 
0 | 
| T162 | 
39055 | 
288 | 
0 | 
0 | 
| T163 | 
12328 | 
47 | 
0 | 
0 | 
| T164 | 
14332 | 
15 | 
0 | 
0 |