Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3520909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4151443

1

T2

1

T3

113

T4

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4230220	1			T1	53		T2	1		T3	101
values[0x0]	1720858	1			T3	58		T4	15		T5	47
values[0x1]	1721274	1			T3	42		T4	12		T5	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2500704	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5171648

1

T1

13

T2

1

T3

155

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27670	1			T1	1		T6	12		T7	4
valid_sources[0x01]	34299	1			T1	1		T3	3		T6	3
valid_sources[0x02]	27319	1			T1	1		T9	1		T15	3
valid_sources[0x03]	28152	1			T1	2		T3	3		T6	2
valid_sources[0x04]	28242	1			T5	22		T6	7		T7	5
valid_sources[0x05]	28358	1			T6	8		T7	4		T9	2
valid_sources[0x06]	29744	1			T1	1		T6	2		T9	3
valid_sources[0x07]	32854	1			T7	3		T9	2		T15	2
valid_sources[0x08]	32059	1			T6	2		T7	1		T15	8
valid_sources[0x09]	29686	1			T6	2		T7	5		T9	2
valid_sources[0x0a]	27855	1			T6	3		T7	6		T15	8
valid_sources[0x0b]	33555	1			T3	5		T6	1		T7	8
valid_sources[0x0c]	35712	1			T6	3		T7	5		T9	2
valid_sources[0x0d]	27172	1			T6	2		T7	1		T9	1
valid_sources[0x0e]	29163	1			T6	2		T7	6		T9	1
valid_sources[0x0f]	28741	1			T1	1		T6	6		T7	9
valid_sources[0x10]	29434	1			T3	3		T6	4		T7	9
valid_sources[0x11]	29616	1			T3	1		T6	3		T7	3
valid_sources[0x12]	29845	1			T6	4		T7	2		T15	2
valid_sources[0x13]	28139	1			T3	2		T6	2		T7	1
valid_sources[0x14]	26678	1			T1	1		T3	5		T6	2
valid_sources[0x15]	27721	1			T6	3		T7	2		T15	8
valid_sources[0x16]	31450	1			T5	1		T6	2		T7	2
valid_sources[0x17]	33769	1			T1	1		T6	5		T7	5
valid_sources[0x18]	28298	1			T1	1		T6	4		T7	1
valid_sources[0x19]	32093	1			T6	4		T7	2		T15	5
valid_sources[0x1a]	24842	1			T3	2		T6	4		T7	6
valid_sources[0x1b]	28244	1			T6	4		T15	3		T25	23
valid_sources[0x1c]	28950	1			T3	4		T6	2		T7	4
valid_sources[0x1d]	29686	1			T6	8		T7	4		T9	2
valid_sources[0x1e]	27617	1			T6	2		T7	7		T9	1
valid_sources[0x1f]	31275	1			T6	1		T15	7		T25	11
valid_sources[0x20]	30779	1			T5	1		T6	5		T7	3
valid_sources[0x21]	28553	1			T6	3		T15	5		T25	38
valid_sources[0x22]	30747	1			T3	2		T6	1		T7	5
valid_sources[0x23]	26298	1			T6	6		T7	6		T9	2
valid_sources[0x24]	27282	1			T6	6		T7	1		T9	1
valid_sources[0x25]	28081	1			T3	2		T6	1		T7	2
valid_sources[0x26]	27546	1			T6	2		T7	2		T15	5
valid_sources[0x27]	30505	1			T6	3		T9	1		T15	4
valid_sources[0x28]	30049	1			T1	1		T6	4		T7	2
valid_sources[0x29]	28438	1			T5	1		T6	2		T7	4
valid_sources[0x2a]	31470	1			T6	2		T7	9		T15	5
valid_sources[0x2b]	30243	1			T6	1		T7	1		T9	2
valid_sources[0x2c]	27973	1			T6	1		T7	7		T14	6
valid_sources[0x2d]	29059	1			T6	1		T15	4		T25	16
valid_sources[0x2e]	30146	1			T5	2		T6	4		T7	6
valid_sources[0x2f]	29655	1			T6	5		T7	3		T15	5
valid_sources[0x30]	28500	1			T1	1		T6	2		T15	6
valid_sources[0x31]	35938	1			T5	22		T6	3		T15	3
valid_sources[0x32]	31570	1			T3	1		T6	8		T9	2
valid_sources[0x33]	26593	1			T3	1		T6	4		T7	2
valid_sources[0x34]	27206	1			T3	3		T6	5		T15	2
valid_sources[0x35]	28779	1			T3	3		T6	8		T7	4
valid_sources[0x36]	31381	1			T1	2		T6	16		T9	1
valid_sources[0x37]	35470	1			T6	2		T15	7		T25	4
valid_sources[0x38]	30087	1			T7	8		T9	1		T15	8
valid_sources[0x39]	28146	1			T3	5		T5	10		T6	1
valid_sources[0x3a]	28238	1			T5	4		T6	5		T7	2
valid_sources[0x3b]	29811	1			T6	1		T7	1		T15	2
valid_sources[0x3c]	26665	1			T6	1		T7	6		T15	5
valid_sources[0x3d]	30784	1			T6	2		T7	1		T15	6
valid_sources[0x3e]	29933	1			T3	8		T6	5		T7	2
valid_sources[0x3f]	28417	1			T6	1		T7	7		T9	1
valid_sources[0x40]	27873	1			T3	1		T6	3		T7	4
valid_sources[0x41]	27700	1			T6	1		T7	3		T9	1
valid_sources[0x42]	32329	1			T5	21		T6	10		T7	14
valid_sources[0x43]	30032	1			T6	9		T7	3		T9	1
valid_sources[0x44]	35092	1			T6	3		T7	6		T9	1
valid_sources[0x45]	31837	1			T6	6		T9	1		T15	3
valid_sources[0x46]	31635	1			T6	4		T7	1		T15	11
valid_sources[0x47]	29075	1			T7	5		T9	1		T38	201
valid_sources[0x48]	32798	1			T1	1		T7	8		T15	7
valid_sources[0x49]	30896	1			T3	1		T6	3		T15	11
valid_sources[0x4a]	30630	1			T6	5		T9	1		T15	9
valid_sources[0x4b]	28125	1			T6	3		T7	2		T15	4
valid_sources[0x4c]	27578	1			T6	11		T9	1		T15	7
valid_sources[0x4d]	29001	1			T6	2		T7	10		T9	1
valid_sources[0x4e]	30434	1			T6	6		T7	1		T15	2
valid_sources[0x4f]	33096	1			T6	3		T7	1		T9	1
valid_sources[0x50]	32013	1			T6	5		T7	5		T9	3
valid_sources[0x51]	25961	1			T1	4		T6	3		T7	1
valid_sources[0x52]	27312	1			T6	1		T7	6		T9	1
valid_sources[0x53]	32126	1			T6	4		T7	6		T9	1
valid_sources[0x54]	30050	1			T6	3		T7	4		T15	9
valid_sources[0x55]	29566	1			T5	8		T6	4		T7	1
valid_sources[0x56]	33470	1			T3	6		T6	1		T15	13
valid_sources[0x57]	30039	1			T6	8		T7	1		T15	5
valid_sources[0x58]	29884	1			T3	5		T6	8		T7	5
valid_sources[0x59]	29322	1			T6	3		T7	6		T15	9
valid_sources[0x5a]	26862	1			T6	5		T7	1		T9	1
valid_sources[0x5b]	30194	1			T3	4		T6	1		T9	1
valid_sources[0x5c]	28256	1			T6	2		T7	5		T9	1
valid_sources[0x5d]	26959	1			T6	1		T7	6		T9	1
valid_sources[0x5e]	32885	1			T6	1		T9	5		T11	1108
valid_sources[0x5f]	29515	1			T6	1		T7	2		T15	11
valid_sources[0x60]	28346	1			T3	4		T5	18		T6	2
valid_sources[0x61]	27639	1			T3	8		T5	9		T7	3
valid_sources[0x62]	29612	1			T6	3		T7	7		T9	2
valid_sources[0x63]	31948	1			T3	3		T6	5		T7	1
valid_sources[0x64]	29448	1			T5	6		T6	6		T15	3
valid_sources[0x65]	29616	1			T6	8		T7	1		T15	11
valid_sources[0x66]	28773	1			T6	3		T7	9		T15	1
valid_sources[0x67]	29821	1			T6	4		T7	3		T9	2
valid_sources[0x68]	35126	1			T3	4		T6	2		T7	4
valid_sources[0x69]	28780	1			T3	2		T6	1		T7	5
valid_sources[0x6a]	32961	1			T1	1		T6	4		T15	3
valid_sources[0x6b]	30261	1			T3	1		T6	3		T7	3
valid_sources[0x6c]	30148	1			T7	5		T9	2		T15	11
valid_sources[0x6d]	30862	1			T6	6		T7	9		T9	1
valid_sources[0x6e]	26709	1			T1	1		T6	4		T7	1
valid_sources[0x6f]	28968	1			T6	1		T7	5		T9	1
valid_sources[0x70]	31371	1			T1	3		T6	3		T7	7
valid_sources[0x71]	27681	1			T3	3		T6	3		T7	10
valid_sources[0x72]	28792	1			T3	2		T6	4		T7	8
valid_sources[0x73]	25061	1			T6	1		T7	6		T9	2
valid_sources[0x74]	28308	1			T6	4		T7	4		T15	5
valid_sources[0x75]	31088	1			T1	1		T6	5		T7	3
valid_sources[0x76]	30458	1			T6	5		T7	1		T9	1
valid_sources[0x77]	30523	1			T6	3		T7	3		T15	3
valid_sources[0x78]	29940	1			T6	5		T7	1		T15	2
valid_sources[0x79]	28769	1			T3	1		T6	8		T7	3
valid_sources[0x7a]	26147	1			T6	3		T9	2		T15	5
valid_sources[0x7b]	25847	1			T5	8		T6	1		T7	4
valid_sources[0x7c]	30009	1			T6	2		T7	2		T9	6
valid_sources[0x7d]	33063	1			T5	11		T6	2		T7	7
valid_sources[0x7e]	27890	1			T6	3		T7	1		T9	2
valid_sources[0x7f]	27701	1			T6	4		T7	8		T15	5
valid_sources[0x80]	29278	1			T6	2		T7	5		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1039148

1

T2

1

T3

13

T4

1

values[0x0]

all_enables

biggest_size

1567983

1

T3

58

T4

14

T5

28

values[0x1]

all_enables

biggest_size

1544312

1

T3

42

T4

7

T5

35