Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3540090

1

T1

53

T4

6

T5

128

full_word

4150442

1

T2

1

T4

22

T5

117

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7690102	1			T1	53		T2	1		T4	28
auto[TlIntgErrCmd]	129	1			T126	8		T127	3		T128	5
auto[TlIntgErrData]	150	1			T126	12		T127	5		T128	8
auto[TlIntgErrBoth]	151	1			T126	10		T127	2		T128	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4232986

1

T1

53

T2

1

T4

1

auto[1]

3457546

1

T4

27

T5

101

T6

876

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3193480	1			T1	53		T5	90		T6	1
auto[TlIntgErrNone]	partial	auto[1]	346225	1			T4	6		T5	38		T6	2
auto[TlIntgErrNone]	full_word	auto[0]	1039323	1			T2	1		T4	1		T5	54
auto[TlIntgErrNone]	full_word	auto[1]	3111074	1			T4	21		T5	63		T6	874
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T126	4		T127	2		T205	2
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T126	3		T127	1		T128	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T128	2		T208	1		T207	2
auto[TlIntgErrCmd]	full_word	auto[1]	12	1			T126	1		T204	1		T205	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T126	3		T127	2		T128	3
auto[TlIntgErrData]	partial	auto[1]	77	1			T126	8		T127	2		T128	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T127	1		T205	1		T206	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T126	1		T206	1		T209	1
auto[TlIntgErrBoth]	partial	auto[0]	66	1			T126	3		T128	4		T204	6
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T126	4		T127	1		T128	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T126	1		T127	1		T210	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T126	2		T205	1		T206	1