Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419546845	2815595	0	0
DepthKnown_A	419546845	419411360	0	0
RvalidKnown_A	419546845	419411360	0	0
WreadyKnown_A	419546845	419411360	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	2815595	0	0
T3	2604	100	0	0
T4	2417	0	0	0
T5	3001	0	0	0
T6	9435	1663	0	0
T7	9250	832	0	0
T8	14054	1663	0	0
T9	48313	0	0	0
T10	8193	0	0	0
T11	10853	832	0	0
T12	1455	0	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	1663	0	0
T18	0	1663	0	0
T38	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419546845	2959848	0	0
DepthKnown_A	419546845	419411360	0	0
RvalidKnown_A	419546845	419411360	0	0
WreadyKnown_A	419546845	419411360	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	2959848	0	0
T3	2604	304	0	0
T4	2417	0	0	0
T5	3001	0	0	0
T6	9435	832	0	0
T7	9250	2523	0	0
T8	14054	832	0	0
T9	48313	0	0	0
T10	8193	0	0	0
T11	10853	832	0	0
T12	1455	0	0	0
T15	0	3814	0	0
T16	0	3751	0	0
T17	0	832	0	0
T18	0	832	0	0
T38	0	453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419546845	192495	0	0
DepthKnown_A	419546845	419411360	0	0
RvalidKnown_A	419546845	419411360	0	0
WreadyKnown_A	419546845	419411360	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	192495	0	0
T3	2604	100	0	0
T4	2417	0	0	0
T5	3001	45	0	0
T6	9435	0	0	0
T7	9250	0	0	0
T8	14054	0	0	0
T9	48313	0	0	0
T10	8193	0	0	0
T11	10853	0	0	0
T12	1455	0	0	0
T15	0	256	0	0
T25	0	626	0	0
T27	0	258	0	0
T30	0	58	0	0
T38	0	100	0	0
T42	0	100	0	0
T43	0	79	0	0
T44	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419546845	440442	0	0
DepthKnown_A	419546845	419411360	0	0
RvalidKnown_A	419546845	419411360	0	0
WreadyKnown_A	419546845	419411360	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	440442	0	0
T3	2604	336	0	0
T4	2417	0	0	0
T5	3001	45	0	0
T6	9435	0	0	0
T7	9250	0	0	0
T8	14054	0	0	0
T9	48313	0	0	0
T10	8193	0	0	0
T11	10853	0	0	0
T12	1455	0	0	0
T15	0	1197	0	0
T25	0	2848	0	0
T27	0	1099	0	0
T30	0	58	0	0
T38	0	461	0	0
T42	0	100	0	0
T43	0	79	0	0
T44	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419546845	6125959	0	0
DepthKnown_A	419546845	419411360	0	0
RvalidKnown_A	419546845	419411360	0	0
WreadyKnown_A	419546845	419411360	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	6125959	0	0
T1	1210	53	0	0
T2	1007	1	0	0
T3	2604	1	0	0
T4	2417	28	0	0
T5	3001	200	0	0
T6	9435	46	0	0
T7	9250	87	0	0
T8	14054	370	0	0
T9	48313	254	0	0
T10	8193	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419546845	13276376	0	0
DepthKnown_A	419546845	419411360	0	0
RvalidKnown_A	419546845	419411360	0	0
WreadyKnown_A	419546845	419411360	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	13276376	0	0
T1	1210	53	0	0
T2	1007	1	0	0
T3	2604	3	0	0
T4	2417	28	0	0
T5	3001	200	0	0
T6	9435	93	0	0
T7	9250	213	0	0
T8	14054	1614	0	0
T9	48313	1123	0	0
T10	8193	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419546845	419411360	0	0
T1	1210	1156	0	0
T2	1007	910	0	0
T3	2604	2504	0	0
T4	2417	2361	0	0
T5	3001	2924	0	0
T6	9435	9385	0	0
T7	9250	9171	0	0
T8	14054	13986	0	0
T9	48313	48237	0	0
T10	8193	5809	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0