Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3406669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4119527

1

T1

1

T3

111

T4

1507

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4134813	1			T1	1		T2	77		T3	101
values[0x0]	1694189	1			T3	48		T4	458		T5	2
values[0x1]	1697194	1			T3	52		T4	432		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2421784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5104412

1

T1

1

T2

35

T3

162

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26230	1			T4	7		T15	3		T16	7
valid_sources[0x01]	41144	1			T4	13		T7	1		T15	2
valid_sources[0x02]	27409	1			T4	7		T42	3		T15	2
valid_sources[0x03]	29071	1			T4	11		T42	2		T15	5
valid_sources[0x04]	29232	1			T4	2		T15	3		T16	7
valid_sources[0x05]	27166	1			T4	10		T42	3		T15	8
valid_sources[0x06]	35154	1			T4	11		T11	1		T15	4
valid_sources[0x07]	27628	1			T4	7		T7	1		T16	4
valid_sources[0x08]	27899	1			T4	8		T7	1		T15	5
valid_sources[0x09]	26334	1			T4	7		T6	1		T15	7
valid_sources[0x0a]	32223	1			T4	8		T16	4		T40	7
valid_sources[0x0b]	31204	1			T4	6		T15	8		T16	5
valid_sources[0x0c]	33683	1			T4	15		T7	1		T42	11
valid_sources[0x0d]	27229	1			T4	6		T15	3		T16	3
valid_sources[0x0e]	28219	1			T4	5		T26	1		T15	2
valid_sources[0x0f]	31145	1			T4	10		T5	1		T42	3
valid_sources[0x10]	26431	1			T4	15		T7	2		T15	2
valid_sources[0x11]	31856	1			T3	1		T4	10		T15	6
valid_sources[0x12]	31210	1			T4	12		T16	3		T40	7
valid_sources[0x13]	27020	1			T4	12		T15	1		T16	7
valid_sources[0x14]	27736	1			T3	12		T4	1		T15	5
valid_sources[0x15]	27478	1			T4	7		T15	4		T16	5
valid_sources[0x16]	25611	1			T4	10		T42	4		T15	3
valid_sources[0x17]	27398	1			T4	10		T42	17		T15	1
valid_sources[0x18]	27909	1			T4	8		T42	3		T15	2
valid_sources[0x19]	26600	1			T4	7		T15	6		T16	1
valid_sources[0x1a]	28802	1			T4	11		T15	9		T16	9
valid_sources[0x1b]	26555	1			T4	14		T15	6		T17	10
valid_sources[0x1c]	28947	1			T4	4		T15	4		T16	3
valid_sources[0x1d]	28395	1			T4	13		T15	6		T16	5
valid_sources[0x1e]	27435	1			T4	10		T16	7		T18	8
valid_sources[0x1f]	28351	1			T4	13		T11	1		T15	1
valid_sources[0x20]	31039	1			T4	2		T15	3		T16	1
valid_sources[0x21]	35252	1			T4	10		T7	3		T16	4
valid_sources[0x22]	28933	1			T4	12		T15	1		T16	4
valid_sources[0x23]	32872	1			T4	6		T11	1		T15	6
valid_sources[0x24]	26729	1			T4	9		T13	1		T15	2
valid_sources[0x25]	29094	1			T3	6		T4	8		T15	1
valid_sources[0x26]	32594	1			T4	6		T11	1		T15	7
valid_sources[0x27]	27611	1			T4	8		T15	2		T16	6
valid_sources[0x28]	28487	1			T4	12		T6	1		T15	3
valid_sources[0x29]	28104	1			T4	9		T15	3		T16	6
valid_sources[0x2a]	26676	1			T4	5		T15	2		T16	3
valid_sources[0x2b]	30617	1			T4	12		T15	4		T16	3
valid_sources[0x2c]	34101	1			T4	5		T11	3		T15	12
valid_sources[0x2d]	27624	1			T4	6		T16	5		T17	48
valid_sources[0x2e]	31298	1			T4	7		T7	1		T15	4
valid_sources[0x2f]	33859	1			T4	5		T42	2		T15	6
valid_sources[0x30]	29338	1			T4	13		T7	3		T15	3
valid_sources[0x31]	28505	1			T4	15		T8	1		T15	3
valid_sources[0x32]	29301	1			T4	9		T15	1		T16	2
valid_sources[0x33]	28533	1			T4	14		T15	5		T16	5
valid_sources[0x34]	32055	1			T4	5		T42	2		T15	7
valid_sources[0x35]	33712	1			T4	13		T15	7		T16	2
valid_sources[0x36]	28112	1			T4	8		T15	7		T16	3
valid_sources[0x37]	28520	1			T4	7		T15	3		T16	3
valid_sources[0x38]	27035	1			T4	9		T40	2		T20	5
valid_sources[0x39]	35407	1			T4	12		T15	1		T16	2
valid_sources[0x3a]	26321	1			T3	3		T4	8		T15	3
valid_sources[0x3b]	28274	1			T4	6		T6	1		T15	7
valid_sources[0x3c]	28331	1			T4	17		T15	10		T16	3
valid_sources[0x3d]	28037	1			T4	12		T15	7		T16	8
valid_sources[0x3e]	26324	1			T4	7		T16	4		T17	7
valid_sources[0x3f]	29364	1			T4	3		T7	2		T15	3
valid_sources[0x40]	29611	1			T4	6		T15	6		T16	7
valid_sources[0x41]	27038	1			T4	8		T15	2		T16	3
valid_sources[0x42]	33268	1			T4	9		T15	12		T16	3
valid_sources[0x43]	31780	1			T4	4		T26	3		T15	5
valid_sources[0x44]	27117	1			T4	11		T15	10		T16	3
valid_sources[0x45]	29787	1			T4	6		T7	1		T15	2
valid_sources[0x46]	26177	1			T4	4		T7	1		T15	8
valid_sources[0x47]	25476	1			T4	1		T11	2		T15	1
valid_sources[0x48]	27256	1			T4	14		T15	3		T16	7
valid_sources[0x49]	28536	1			T4	10		T15	6		T16	5
valid_sources[0x4a]	31215	1			T4	4		T12	7		T15	9
valid_sources[0x4b]	27184	1			T4	6		T15	5		T16	8
valid_sources[0x4c]	36992	1			T4	5		T7	1		T10	63
valid_sources[0x4d]	30698	1			T4	3		T42	2		T15	4
valid_sources[0x4e]	27892	1			T4	8		T15	2		T16	6
valid_sources[0x4f]	33049	1			T4	5		T42	5		T15	3
valid_sources[0x50]	30933	1			T4	10		T7	1		T26	1
valid_sources[0x51]	29776	1			T4	14		T15	11		T16	6
valid_sources[0x52]	31120	1			T4	16		T16	2		T17	10
valid_sources[0x53]	27274	1			T4	8		T42	2		T15	3
valid_sources[0x54]	29759	1			T4	3		T11	1		T15	3
valid_sources[0x55]	26370	1			T4	8		T15	3		T17	31
valid_sources[0x56]	29981	1			T4	13		T42	14		T15	1
valid_sources[0x57]	30133	1			T4	5		T15	2		T16	7
valid_sources[0x58]	27250	1			T4	9		T12	13		T15	12
valid_sources[0x59]	27549	1			T4	9		T15	1		T16	6
valid_sources[0x5a]	30130	1			T4	7		T15	2		T16	3
valid_sources[0x5b]	28773	1			T4	3		T15	1		T16	5
valid_sources[0x5c]	31639	1			T3	3		T4	8		T15	3
valid_sources[0x5d]	43703	1			T4	4		T11	1		T15	2
valid_sources[0x5e]	29387	1			T4	13		T11	1		T15	2
valid_sources[0x5f]	28832	1			T3	5		T4	3		T15	6
valid_sources[0x60]	27064	1			T4	5		T15	4		T16	6
valid_sources[0x61]	28547	1			T4	19		T7	1		T42	4
valid_sources[0x62]	30957	1			T4	6		T15	7		T16	3
valid_sources[0x63]	27452	1			T4	6		T42	4		T15	10
valid_sources[0x64]	29928	1			T4	12		T15	7		T16	4
valid_sources[0x65]	30187	1			T4	6		T11	1		T15	3
valid_sources[0x66]	27367	1			T4	11		T15	12		T16	4
valid_sources[0x67]	29719	1			T4	5		T7	1		T15	1
valid_sources[0x68]	28185	1			T4	12		T11	1		T15	2
valid_sources[0x69]	33132	1			T3	21		T4	11		T11	2
valid_sources[0x6a]	30513	1			T4	15		T7	1		T15	2
valid_sources[0x6b]	28144	1			T4	7		T15	3		T16	4
valid_sources[0x6c]	28180	1			T4	8		T15	3		T16	1
valid_sources[0x6d]	26726	1			T4	5		T15	5		T16	2
valid_sources[0x6e]	37077	1			T2	77		T4	12		T15	6
valid_sources[0x6f]	29756	1			T4	10		T7	1		T42	8
valid_sources[0x70]	27428	1			T4	8		T15	3		T16	1
valid_sources[0x71]	29377	1			T4	8		T16	3		T17	12
valid_sources[0x72]	29259	1			T4	4		T11	1		T15	2
valid_sources[0x73]	27046	1			T4	4		T7	1		T12	7
valid_sources[0x74]	26645	1			T4	18		T15	3		T16	4
valid_sources[0x75]	29833	1			T4	21		T16	3		T17	19
valid_sources[0x76]	32513	1			T4	6		T15	4		T16	1
valid_sources[0x77]	29133	1			T3	12		T4	9		T14	1
valid_sources[0x78]	27306	1			T4	4		T15	4		T16	4
valid_sources[0x79]	27421	1			T4	9		T16	10		T17	5
valid_sources[0x7a]	29297	1			T4	10		T11	1		T15	5
valid_sources[0x7b]	30793	1			T4	7		T11	1		T42	2
valid_sources[0x7c]	27242	1			T4	7		T16	4		T40	2
valid_sources[0x7d]	27310	1			T4	6		T15	2		T16	1
valid_sources[0x7e]	31768	1			T4	8		T6	2		T15	6
valid_sources[0x7f]	30041	1			T4	14		T42	2		T15	7
valid_sources[0x80]	26037	1			T4	10		T15	4		T16	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1043303

1

T1

1

T3

11

T4

622

values[0x0]

all_enables

biggest_size

1548862

1

T3

48

T4

458

T5

2

values[0x1]

all_enables

biggest_size

1527362

1

T3

52

T4

427

T5

8