Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3434033

1

T2

77

T4

682

T5

4

full_word

4119030

1

T1

1

T4

1507

T5

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7552683	1			T1	1		T2	77		T4	2189
auto[TlIntgErrCmd]	131	1			T138	3		T139	5		T140	15
auto[TlIntgErrData]	131	1			T138	4		T139	10		T140	7
auto[TlIntgErrBoth]	118	1			T138	3		T139	5		T140	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4139003

1

T1

1

T2

77

T4

1299

auto[1]

3414060

1

T4

890

T5

13

T6

5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3095248	1			T2	77		T4	677		T5	1
auto[TlIntgErrNone]	partial	auto[1]	338439	1			T4	5		T5	3		T6	3
auto[TlIntgErrNone]	full_word	auto[0]	1043588	1			T1	1		T4	622		T8	1
auto[TlIntgErrNone]	full_word	auto[1]	3075408	1			T4	885		T5	10		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T138	2		T139	2		T140	5
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T138	1		T139	3		T140	9
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T225	1		T221	1		T226	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T140	1		T227	1		T228	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T138	3		T139	6		T140	4
auto[TlIntgErrData]	partial	auto[1]	62	1			T138	1		T139	4		T140	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T188	1		T189	1		T229	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T140	1		T230	1		T224	2
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T138	2		T139	2		T140	3
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T138	1		T139	2		T140	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T229	1		T224	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T139	1		T189	1		T222	1