Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	434166640	2786675	0	0
DepthKnown_A	434166640	434033703	0	0
RvalidKnown_A	434166640	434033703	0	0
WreadyKnown_A	434166640	434033703	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	2786675	0	0
T3	1601	100	0	0
T4	52237	1663	0	0
T5	8499	0	0	0
T6	1062	0	0	0
T7	6481	0	0	0
T8	2070	0	0	0
T9	965	0	0	0
T10	2589	0	0	0
T11	5937	0	0	0
T12	1813	0	0	0
T15	0	832	0	0
T16	0	1663	0	0
T17	0	1663	0	0
T20	0	1663	0	0
T21	0	832	0	0
T39	0	100	0	0
T40	0	1663	0	0
T42	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	434166640	3105725	0	0
DepthKnown_A	434166640	434033703	0	0
RvalidKnown_A	434166640	434033703	0	0
WreadyKnown_A	434166640	434033703	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	3105725	0	0
T3	1601	100	0	0
T4	52237	832	0	0
T5	8499	0	0	0
T6	1062	0	0	0
T7	6481	0	0	0
T8	2070	0	0	0
T9	965	0	0	0
T10	2589	0	0	0
T11	5937	0	0	0
T12	1813	0	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T20	0	832	0	0
T21	0	2710	0	0
T39	0	310	0	0
T40	0	832	0	0
T42	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	434166640	192571	0	0
DepthKnown_A	434166640	434033703	0	0
RvalidKnown_A	434166640	434033703	0	0
WreadyKnown_A	434166640	434033703	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	192571	0	0
T3	1601	100	0	0
T4	52237	0	0	0
T5	8499	0	0	0
T6	1062	0	0	0
T7	6481	0	0	0
T8	2070	0	0	0
T9	965	0	0	0
T10	2589	10	0	0
T11	5937	0	0	0
T12	1813	0	0	0
T16	0	64	0	0
T18	0	16	0	0
T27	0	28	0	0
T29	0	134	0	0
T39	0	100	0	0
T42	0	100	0	0
T49	0	100	0	0
T50	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	434166640	417274	0	0
DepthKnown_A	434166640	434033703	0	0
RvalidKnown_A	434166640	434033703	0	0
WreadyKnown_A	434166640	434033703	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	417274	0	0
T3	1601	100	0	0
T4	52237	0	0	0
T5	8499	0	0	0
T6	1062	0	0	0
T7	6481	0	0	0
T8	2070	0	0	0
T9	965	0	0	0
T10	2589	10	0	0
T11	5937	0	0	0
T12	1813	0	0	0
T16	0	204	0	0
T18	0	16	0	0
T27	0	28	0	0
T29	0	134	0	0
T39	0	315	0	0
T42	0	100	0	0
T49	0	100	0	0
T50	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	434166640	5940973	0	0
DepthKnown_A	434166640	434033703	0	0
RvalidKnown_A	434166640	434033703	0	0
WreadyKnown_A	434166640	434033703	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	5940973	0	0
T1	1580	1	0	0
T2	1870	77	0	0
T3	1601	1	0	0
T4	52237	1357	0	0
T5	8499	14	0	0
T6	1062	6	0	0
T7	6481	44	0	0
T8	2070	12	0	0
T9	965	81	0	0
T10	2589	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	434166640	12387061	0	0
DepthKnown_A	434166640	434033703	0	0
RvalidKnown_A	434166640	434033703	0	0
WreadyKnown_A	434166640	434033703	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	12387061	0	0
T1	1580	1	0	0
T2	1870	247	0	0
T3	1601	1	0	0
T4	52237	1357	0	0
T5	8499	14	0	0
T6	1062	6	0	0
T7	6481	231	0	0
T8	2070	12	0	0
T9	965	81	0	0
T10	2589	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434166640	434033703	0	0
T1	1580	1522	0	0
T2	1870	1809	0	0
T3	1601	1546	0	0
T4	52237	52179	0	0
T5	8499	8423	0	0
T6	1062	994	0	0
T7	6481	6420	0	0
T8	2070	2002	0	0
T9	965	894	0	0
T10	2589	2527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0