Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4221 |
0 |
0 |
T134 |
26970 |
313 |
0 |
0 |
T135 |
7986 |
5 |
0 |
0 |
T136 |
23327 |
302 |
0 |
0 |
T137 |
6914 |
318 |
0 |
0 |
T138 |
27915 |
2 |
0 |
0 |
T143 |
11663 |
146 |
0 |
0 |
T144 |
3715 |
107 |
0 |
0 |
T147 |
2134 |
2 |
0 |
0 |
T148 |
3778 |
6 |
0 |
0 |
T149 |
5309 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
3998 |
0 |
0 |
T116 |
4662 |
6 |
0 |
0 |
T117 |
5037 |
12 |
0 |
0 |
T140 |
108731 |
110 |
0 |
0 |
T159 |
11207 |
20 |
0 |
0 |
T184 |
19913 |
46 |
0 |
0 |
T185 |
117484 |
700 |
0 |
0 |
T186 |
7108 |
18 |
0 |
0 |
T187 |
11385 |
17 |
0 |
0 |
T188 |
63162 |
47 |
0 |
0 |
T189 |
66727 |
61 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4089 |
0 |
0 |
T116 |
4662 |
16 |
0 |
0 |
T117 |
5037 |
9 |
0 |
0 |
T140 |
108731 |
103 |
0 |
0 |
T159 |
11207 |
12 |
0 |
0 |
T184 |
19913 |
77 |
0 |
0 |
T185 |
117484 |
740 |
0 |
0 |
T186 |
7108 |
19 |
0 |
0 |
T187 |
11385 |
17 |
0 |
0 |
T188 |
63162 |
33 |
0 |
0 |
T190 |
6548 |
7 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4686 |
0 |
0 |
T116 |
4662 |
22 |
0 |
0 |
T117 |
5037 |
6 |
0 |
0 |
T140 |
108731 |
237 |
0 |
0 |
T159 |
11207 |
15 |
0 |
0 |
T184 |
19913 |
87 |
0 |
0 |
T185 |
117484 |
718 |
0 |
0 |
T186 |
7108 |
22 |
0 |
0 |
T187 |
11385 |
37 |
0 |
0 |
T188 |
63162 |
72 |
0 |
0 |
T190 |
6548 |
9 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
14124 |
0 |
0 |
T116 |
4662 |
13 |
0 |
0 |
T117 |
5037 |
9 |
0 |
0 |
T140 |
108731 |
2699 |
0 |
0 |
T159 |
11207 |
132 |
0 |
0 |
T184 |
19913 |
41 |
0 |
0 |
T185 |
117484 |
765 |
0 |
0 |
T186 |
7108 |
8 |
0 |
0 |
T187 |
11385 |
241 |
0 |
0 |
T188 |
63162 |
415 |
0 |
0 |
T190 |
6548 |
149 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
12908 |
0 |
0 |
T116 |
4662 |
9 |
0 |
0 |
T117 |
5037 |
16 |
0 |
0 |
T140 |
108731 |
1747 |
0 |
0 |
T159 |
11207 |
249 |
0 |
0 |
T184 |
19913 |
70 |
0 |
0 |
T185 |
117484 |
681 |
0 |
0 |
T186 |
7108 |
47 |
0 |
0 |
T187 |
11385 |
130 |
0 |
0 |
T188 |
63162 |
560 |
0 |
0 |
T190 |
6548 |
115 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
13734 |
0 |
0 |
T116 |
4662 |
19 |
0 |
0 |
T117 |
5037 |
9 |
0 |
0 |
T140 |
108731 |
1837 |
0 |
0 |
T159 |
11207 |
152 |
0 |
0 |
T184 |
19913 |
51 |
0 |
0 |
T185 |
117484 |
723 |
0 |
0 |
T186 |
7108 |
2 |
0 |
0 |
T187 |
11385 |
23 |
0 |
0 |
T188 |
63162 |
542 |
0 |
0 |
T190 |
6548 |
119 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
11795 |
0 |
0 |
T116 |
4662 |
15 |
0 |
0 |
T117 |
5037 |
14 |
0 |
0 |
T140 |
108731 |
1659 |
0 |
0 |
T159 |
11207 |
247 |
0 |
0 |
T184 |
19913 |
78 |
0 |
0 |
T185 |
117484 |
768 |
0 |
0 |
T186 |
7108 |
17 |
0 |
0 |
T187 |
11385 |
14 |
0 |
0 |
T188 |
63162 |
644 |
0 |
0 |
T190 |
6548 |
127 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
13023 |
0 |
0 |
T116 |
4662 |
8 |
0 |
0 |
T117 |
5037 |
12 |
0 |
0 |
T134 |
26970 |
4 |
0 |
0 |
T140 |
108731 |
2118 |
0 |
0 |
T159 |
11207 |
246 |
0 |
0 |
T184 |
19913 |
102 |
0 |
0 |
T185 |
117484 |
693 |
0 |
0 |
T186 |
7108 |
11 |
0 |
0 |
T187 |
11385 |
214 |
0 |
0 |
T188 |
63162 |
547 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
13753 |
0 |
0 |
T116 |
4662 |
6 |
0 |
0 |
T117 |
5037 |
12 |
0 |
0 |
T140 |
108731 |
2128 |
0 |
0 |
T159 |
11207 |
229 |
0 |
0 |
T184 |
19913 |
95 |
0 |
0 |
T185 |
117484 |
731 |
0 |
0 |
T186 |
7108 |
13 |
0 |
0 |
T187 |
11385 |
142 |
0 |
0 |
T188 |
63162 |
686 |
0 |
0 |
T190 |
6548 |
8 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
12932 |
0 |
0 |
T116 |
4662 |
8 |
0 |
0 |
T117 |
5037 |
7 |
0 |
0 |
T140 |
108731 |
1949 |
0 |
0 |
T159 |
11207 |
135 |
0 |
0 |
T184 |
19913 |
57 |
0 |
0 |
T185 |
117484 |
715 |
0 |
0 |
T186 |
7108 |
32 |
0 |
0 |
T187 |
11385 |
206 |
0 |
0 |
T188 |
63162 |
807 |
0 |
0 |
T190 |
6548 |
133 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
12070 |
0 |
0 |
T116 |
4662 |
13 |
0 |
0 |
T117 |
5037 |
12 |
0 |
0 |
T140 |
108731 |
1738 |
0 |
0 |
T159 |
11207 |
120 |
0 |
0 |
T184 |
19913 |
68 |
0 |
0 |
T185 |
117484 |
747 |
0 |
0 |
T186 |
7108 |
5 |
0 |
0 |
T187 |
11385 |
15 |
0 |
0 |
T188 |
63162 |
769 |
0 |
0 |
T190 |
6548 |
140 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7245 |
0 |
0 |
T116 |
4662 |
5 |
0 |
0 |
T117 |
5037 |
8 |
0 |
0 |
T134 |
26970 |
8 |
0 |
0 |
T140 |
108731 |
788 |
0 |
0 |
T159 |
11207 |
98 |
0 |
0 |
T184 |
19913 |
67 |
0 |
0 |
T185 |
117484 |
675 |
0 |
0 |
T186 |
7108 |
35 |
0 |
0 |
T187 |
11385 |
21 |
0 |
0 |
T188 |
63162 |
298 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7839 |
0 |
0 |
T116 |
4662 |
13 |
0 |
0 |
T117 |
5037 |
8 |
0 |
0 |
T140 |
108731 |
820 |
0 |
0 |
T159 |
11207 |
103 |
0 |
0 |
T184 |
19913 |
49 |
0 |
0 |
T185 |
117484 |
749 |
0 |
0 |
T186 |
7108 |
25 |
0 |
0 |
T187 |
11385 |
78 |
0 |
0 |
T188 |
63162 |
159 |
0 |
0 |
T190 |
6548 |
5 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7794 |
0 |
0 |
T116 |
4662 |
17 |
0 |
0 |
T117 |
5037 |
20 |
0 |
0 |
T140 |
108731 |
609 |
0 |
0 |
T159 |
11207 |
92 |
0 |
0 |
T184 |
19913 |
76 |
0 |
0 |
T185 |
117484 |
713 |
0 |
0 |
T186 |
7108 |
6 |
0 |
0 |
T187 |
11385 |
7 |
0 |
0 |
T188 |
63162 |
295 |
0 |
0 |
T190 |
6548 |
8 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7223 |
0 |
0 |
T116 |
4662 |
6 |
0 |
0 |
T117 |
5037 |
4 |
0 |
0 |
T140 |
108731 |
659 |
0 |
0 |
T159 |
11207 |
70 |
0 |
0 |
T184 |
19913 |
49 |
0 |
0 |
T185 |
117484 |
801 |
0 |
0 |
T186 |
7108 |
24 |
0 |
0 |
T187 |
11385 |
54 |
0 |
0 |
T188 |
63162 |
182 |
0 |
0 |
T190 |
6548 |
5 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7275 |
0 |
0 |
T116 |
4662 |
13 |
0 |
0 |
T117 |
5037 |
23 |
0 |
0 |
T140 |
108731 |
781 |
0 |
0 |
T159 |
11207 |
107 |
0 |
0 |
T184 |
19913 |
120 |
0 |
0 |
T185 |
117484 |
718 |
0 |
0 |
T186 |
7108 |
42 |
0 |
0 |
T187 |
11385 |
72 |
0 |
0 |
T188 |
63162 |
192 |
0 |
0 |
T190 |
6548 |
51 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
8185 |
0 |
0 |
T116 |
4662 |
13 |
0 |
0 |
T117 |
5037 |
16 |
0 |
0 |
T140 |
108731 |
743 |
0 |
0 |
T159 |
11207 |
102 |
0 |
0 |
T184 |
19913 |
77 |
0 |
0 |
T185 |
117484 |
721 |
0 |
0 |
T186 |
7108 |
32 |
0 |
0 |
T187 |
11385 |
102 |
0 |
0 |
T188 |
63162 |
434 |
0 |
0 |
T190 |
6548 |
57 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7217 |
0 |
0 |
T116 |
4662 |
7 |
0 |
0 |
T117 |
5037 |
6 |
0 |
0 |
T140 |
108731 |
887 |
0 |
0 |
T159 |
11207 |
101 |
0 |
0 |
T184 |
19913 |
41 |
0 |
0 |
T185 |
117484 |
712 |
0 |
0 |
T186 |
7108 |
10 |
0 |
0 |
T187 |
11385 |
60 |
0 |
0 |
T188 |
63162 |
160 |
0 |
0 |
T190 |
6548 |
6 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7681 |
0 |
0 |
T116 |
4662 |
12 |
0 |
0 |
T117 |
5037 |
8 |
0 |
0 |
T140 |
108731 |
655 |
0 |
0 |
T159 |
11207 |
51 |
0 |
0 |
T184 |
19913 |
53 |
0 |
0 |
T185 |
117484 |
749 |
0 |
0 |
T186 |
7108 |
8 |
0 |
0 |
T187 |
11385 |
101 |
0 |
0 |
T188 |
63162 |
300 |
0 |
0 |
T190 |
6548 |
56 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7717 |
0 |
0 |
T116 |
4662 |
6 |
0 |
0 |
T117 |
5037 |
6 |
0 |
0 |
T140 |
108731 |
842 |
0 |
0 |
T159 |
11207 |
50 |
0 |
0 |
T184 |
19913 |
90 |
0 |
0 |
T185 |
117484 |
802 |
0 |
0 |
T186 |
7108 |
51 |
0 |
0 |
T187 |
11385 |
17 |
0 |
0 |
T188 |
63162 |
326 |
0 |
0 |
T190 |
6548 |
18 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7453 |
0 |
0 |
T116 |
4662 |
10 |
0 |
0 |
T117 |
5037 |
6 |
0 |
0 |
T140 |
108731 |
769 |
0 |
0 |
T159 |
11207 |
42 |
0 |
0 |
T184 |
19913 |
60 |
0 |
0 |
T185 |
117484 |
765 |
0 |
0 |
T186 |
7108 |
7 |
0 |
0 |
T187 |
11385 |
99 |
0 |
0 |
T188 |
63162 |
254 |
0 |
0 |
T190 |
6548 |
52 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7887 |
0 |
0 |
T116 |
4662 |
7 |
0 |
0 |
T117 |
5037 |
8 |
0 |
0 |
T140 |
108731 |
870 |
0 |
0 |
T159 |
11207 |
12 |
0 |
0 |
T184 |
19913 |
79 |
0 |
0 |
T185 |
117484 |
673 |
0 |
0 |
T186 |
7108 |
33 |
0 |
0 |
T187 |
11385 |
115 |
0 |
0 |
T188 |
63162 |
253 |
0 |
0 |
T190 |
6548 |
61 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7403 |
0 |
0 |
T116 |
4662 |
19 |
0 |
0 |
T117 |
5037 |
17 |
0 |
0 |
T140 |
108731 |
745 |
0 |
0 |
T159 |
11207 |
97 |
0 |
0 |
T184 |
19913 |
76 |
0 |
0 |
T185 |
117484 |
754 |
0 |
0 |
T186 |
7108 |
10 |
0 |
0 |
T187 |
11385 |
10 |
0 |
0 |
T188 |
63162 |
253 |
0 |
0 |
T190 |
6548 |
30 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7691 |
0 |
0 |
T116 |
4662 |
15 |
0 |
0 |
T117 |
5037 |
8 |
0 |
0 |
T140 |
108731 |
776 |
0 |
0 |
T159 |
11207 |
15 |
0 |
0 |
T184 |
19913 |
69 |
0 |
0 |
T185 |
117484 |
729 |
0 |
0 |
T186 |
7108 |
8 |
0 |
0 |
T187 |
11385 |
6 |
0 |
0 |
T188 |
63162 |
359 |
0 |
0 |
T190 |
6548 |
10 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7893 |
0 |
0 |
T116 |
4662 |
9 |
0 |
0 |
T117 |
5037 |
11 |
0 |
0 |
T140 |
108731 |
872 |
0 |
0 |
T159 |
11207 |
166 |
0 |
0 |
T184 |
19913 |
76 |
0 |
0 |
T185 |
117484 |
731 |
0 |
0 |
T186 |
7108 |
13 |
0 |
0 |
T187 |
11385 |
65 |
0 |
0 |
T188 |
63162 |
307 |
0 |
0 |
T190 |
6548 |
71 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7511 |
0 |
0 |
T116 |
4662 |
7 |
0 |
0 |
T117 |
5037 |
18 |
0 |
0 |
T140 |
108731 |
653 |
0 |
0 |
T159 |
11207 |
101 |
0 |
0 |
T184 |
19913 |
76 |
0 |
0 |
T185 |
117484 |
735 |
0 |
0 |
T186 |
7108 |
48 |
0 |
0 |
T187 |
11385 |
105 |
0 |
0 |
T188 |
63162 |
282 |
0 |
0 |
T190 |
6548 |
3 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7002 |
0 |
0 |
T116 |
4662 |
25 |
0 |
0 |
T117 |
5037 |
4 |
0 |
0 |
T140 |
108731 |
702 |
0 |
0 |
T159 |
11207 |
5 |
0 |
0 |
T184 |
19913 |
36 |
0 |
0 |
T185 |
117484 |
700 |
0 |
0 |
T186 |
7108 |
10 |
0 |
0 |
T187 |
11385 |
50 |
0 |
0 |
T188 |
63162 |
333 |
0 |
0 |
T190 |
6548 |
55 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7765 |
0 |
0 |
T116 |
4662 |
12 |
0 |
0 |
T117 |
5037 |
12 |
0 |
0 |
T140 |
108731 |
789 |
0 |
0 |
T159 |
11207 |
102 |
0 |
0 |
T184 |
19913 |
87 |
0 |
0 |
T185 |
117484 |
745 |
0 |
0 |
T186 |
7108 |
51 |
0 |
0 |
T187 |
11385 |
102 |
0 |
0 |
T188 |
63162 |
240 |
0 |
0 |
T190 |
6548 |
72 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7650 |
0 |
0 |
T116 |
4662 |
5 |
0 |
0 |
T117 |
5037 |
13 |
0 |
0 |
T140 |
108731 |
768 |
0 |
0 |
T159 |
11207 |
80 |
0 |
0 |
T184 |
19913 |
15 |
0 |
0 |
T185 |
117484 |
701 |
0 |
0 |
T186 |
7108 |
48 |
0 |
0 |
T187 |
11385 |
118 |
0 |
0 |
T188 |
63162 |
196 |
0 |
0 |
T190 |
6548 |
74 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7741 |
0 |
0 |
T116 |
4662 |
13 |
0 |
0 |
T117 |
5037 |
19 |
0 |
0 |
T140 |
108731 |
987 |
0 |
0 |
T159 |
11207 |
52 |
0 |
0 |
T184 |
19913 |
64 |
0 |
0 |
T185 |
117484 |
759 |
0 |
0 |
T186 |
7108 |
6 |
0 |
0 |
T187 |
11385 |
115 |
0 |
0 |
T188 |
63162 |
288 |
0 |
0 |
T190 |
6548 |
56 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7797 |
0 |
0 |
T116 |
4662 |
19 |
0 |
0 |
T117 |
5037 |
10 |
0 |
0 |
T140 |
108731 |
1012 |
0 |
0 |
T159 |
11207 |
20 |
0 |
0 |
T184 |
19913 |
89 |
0 |
0 |
T185 |
117484 |
759 |
0 |
0 |
T186 |
7108 |
45 |
0 |
0 |
T187 |
11385 |
110 |
0 |
0 |
T188 |
63162 |
427 |
0 |
0 |
T190 |
6548 |
55 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7206 |
0 |
0 |
T116 |
4662 |
25 |
0 |
0 |
T117 |
5037 |
2 |
0 |
0 |
T140 |
108731 |
737 |
0 |
0 |
T159 |
11207 |
91 |
0 |
0 |
T184 |
19913 |
63 |
0 |
0 |
T185 |
117484 |
720 |
0 |
0 |
T186 |
7108 |
30 |
0 |
0 |
T187 |
11385 |
19 |
0 |
0 |
T188 |
63162 |
265 |
0 |
0 |
T190 |
6548 |
44 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7827 |
0 |
0 |
T116 |
4662 |
15 |
0 |
0 |
T117 |
5037 |
7 |
0 |
0 |
T140 |
108731 |
908 |
0 |
0 |
T159 |
11207 |
49 |
0 |
0 |
T184 |
19913 |
45 |
0 |
0 |
T185 |
117484 |
739 |
0 |
0 |
T186 |
7108 |
31 |
0 |
0 |
T187 |
11385 |
63 |
0 |
0 |
T188 |
63162 |
261 |
0 |
0 |
T190 |
6548 |
62 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7405 |
0 |
0 |
T116 |
4662 |
13 |
0 |
0 |
T117 |
5037 |
16 |
0 |
0 |
T140 |
108731 |
826 |
0 |
0 |
T159 |
11207 |
178 |
0 |
0 |
T184 |
19913 |
104 |
0 |
0 |
T185 |
117484 |
787 |
0 |
0 |
T186 |
7108 |
19 |
0 |
0 |
T187 |
11385 |
20 |
0 |
0 |
T188 |
63162 |
187 |
0 |
0 |
T190 |
6548 |
42 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
7868 |
0 |
0 |
T116 |
4662 |
8 |
0 |
0 |
T117 |
5037 |
10 |
0 |
0 |
T140 |
108731 |
802 |
0 |
0 |
T159 |
11207 |
122 |
0 |
0 |
T184 |
19913 |
149 |
0 |
0 |
T185 |
117484 |
711 |
0 |
0 |
T186 |
7108 |
9 |
0 |
0 |
T187 |
11385 |
20 |
0 |
0 |
T188 |
63162 |
329 |
0 |
0 |
T190 |
6548 |
45 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4484 |
0 |
0 |
T116 |
4662 |
19 |
0 |
0 |
T117 |
5037 |
11 |
0 |
0 |
T140 |
108731 |
209 |
0 |
0 |
T159 |
11207 |
9 |
0 |
0 |
T184 |
19913 |
67 |
0 |
0 |
T185 |
117484 |
756 |
0 |
0 |
T186 |
7108 |
7 |
0 |
0 |
T187 |
11385 |
26 |
0 |
0 |
T188 |
63162 |
56 |
0 |
0 |
T190 |
6548 |
12 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4413 |
0 |
0 |
T116 |
4662 |
3 |
0 |
0 |
T117 |
5037 |
4 |
0 |
0 |
T140 |
108731 |
214 |
0 |
0 |
T159 |
11207 |
34 |
0 |
0 |
T184 |
19913 |
46 |
0 |
0 |
T185 |
117484 |
738 |
0 |
0 |
T186 |
7108 |
26 |
0 |
0 |
T187 |
11385 |
31 |
0 |
0 |
T188 |
63162 |
59 |
0 |
0 |
T190 |
6548 |
4 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4401 |
0 |
0 |
T116 |
4662 |
15 |
0 |
0 |
T117 |
5037 |
16 |
0 |
0 |
T140 |
108731 |
177 |
0 |
0 |
T159 |
11207 |
17 |
0 |
0 |
T184 |
19913 |
49 |
0 |
0 |
T185 |
117484 |
700 |
0 |
0 |
T186 |
7108 |
8 |
0 |
0 |
T187 |
11385 |
10 |
0 |
0 |
T188 |
63162 |
84 |
0 |
0 |
T190 |
6548 |
15 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4459 |
0 |
0 |
T116 |
4662 |
4 |
0 |
0 |
T117 |
5037 |
16 |
0 |
0 |
T140 |
108731 |
137 |
0 |
0 |
T159 |
11207 |
30 |
0 |
0 |
T184 |
19913 |
74 |
0 |
0 |
T185 |
117484 |
760 |
0 |
0 |
T186 |
7108 |
15 |
0 |
0 |
T187 |
11385 |
19 |
0 |
0 |
T188 |
63162 |
67 |
0 |
0 |
T190 |
6548 |
6 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
5218 |
0 |
0 |
T116 |
4662 |
9 |
0 |
0 |
T117 |
5037 |
22 |
0 |
0 |
T140 |
108731 |
302 |
0 |
0 |
T159 |
11207 |
47 |
0 |
0 |
T184 |
19913 |
55 |
0 |
0 |
T185 |
117484 |
734 |
0 |
0 |
T186 |
7108 |
38 |
0 |
0 |
T187 |
11385 |
15 |
0 |
0 |
T188 |
63162 |
106 |
0 |
0 |
T190 |
6548 |
14 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
6923 |
0 |
0 |
T36 |
6543 |
31 |
0 |
0 |
T37 |
0 |
82 |
0 |
0 |
T120 |
282365 |
0 |
0 |
0 |
T126 |
0 |
10 |
0 |
0 |
T142 |
25551 |
0 |
0 |
0 |
T191 |
0 |
47 |
0 |
0 |
T192 |
0 |
3 |
0 |
0 |
T193 |
0 |
37 |
0 |
0 |
T194 |
0 |
72 |
0 |
0 |
T195 |
0 |
56 |
0 |
0 |
T196 |
0 |
14 |
0 |
0 |
T197 |
0 |
35 |
0 |
0 |
T198 |
43323 |
0 |
0 |
0 |
T199 |
869599 |
0 |
0 |
0 |
T200 |
1276 |
0 |
0 |
0 |
T201 |
496957 |
0 |
0 |
0 |
T202 |
5506 |
0 |
0 |
0 |
T203 |
2704 |
0 |
0 |
0 |
T204 |
95240 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4552 |
0 |
0 |
T116 |
4662 |
19 |
0 |
0 |
T117 |
5037 |
16 |
0 |
0 |
T140 |
108731 |
155 |
0 |
0 |
T159 |
11207 |
16 |
0 |
0 |
T184 |
19913 |
134 |
0 |
0 |
T185 |
117484 |
749 |
0 |
0 |
T186 |
7108 |
19 |
0 |
0 |
T187 |
11385 |
15 |
0 |
0 |
T188 |
63162 |
59 |
0 |
0 |
T190 |
6548 |
10 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4428 |
0 |
0 |
T116 |
4662 |
12 |
0 |
0 |
T117 |
5037 |
11 |
0 |
0 |
T140 |
108731 |
159 |
0 |
0 |
T159 |
11207 |
8 |
0 |
0 |
T184 |
19913 |
68 |
0 |
0 |
T185 |
117484 |
762 |
0 |
0 |
T186 |
7108 |
4 |
0 |
0 |
T187 |
11385 |
7 |
0 |
0 |
T188 |
63162 |
83 |
0 |
0 |
T190 |
6548 |
15 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4327 |
0 |
0 |
T116 |
4662 |
19 |
0 |
0 |
T117 |
5037 |
7 |
0 |
0 |
T140 |
108731 |
119 |
0 |
0 |
T159 |
11207 |
11 |
0 |
0 |
T184 |
19913 |
124 |
0 |
0 |
T185 |
117484 |
804 |
0 |
0 |
T186 |
7108 |
20 |
0 |
0 |
T187 |
11385 |
20 |
0 |
0 |
T188 |
63162 |
64 |
0 |
0 |
T190 |
6548 |
9 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4254 |
0 |
0 |
T116 |
4662 |
24 |
0 |
0 |
T117 |
5037 |
6 |
0 |
0 |
T136 |
23327 |
5 |
0 |
0 |
T140 |
108731 |
98 |
0 |
0 |
T159 |
11207 |
12 |
0 |
0 |
T184 |
19913 |
47 |
0 |
0 |
T185 |
117484 |
778 |
0 |
0 |
T186 |
7108 |
21 |
0 |
0 |
T187 |
11385 |
7 |
0 |
0 |
T188 |
63162 |
45 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4342 |
0 |
0 |
T116 |
4662 |
5 |
0 |
0 |
T117 |
5037 |
3 |
0 |
0 |
T140 |
108731 |
123 |
0 |
0 |
T159 |
11207 |
11 |
0 |
0 |
T184 |
19913 |
57 |
0 |
0 |
T185 |
117484 |
845 |
0 |
0 |
T186 |
7108 |
24 |
0 |
0 |
T187 |
11385 |
11 |
0 |
0 |
T188 |
63162 |
33 |
0 |
0 |
T190 |
6548 |
8 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4088 |
0 |
0 |
T116 |
4662 |
13 |
0 |
0 |
T117 |
5037 |
16 |
0 |
0 |
T140 |
108731 |
123 |
0 |
0 |
T159 |
11207 |
13 |
0 |
0 |
T184 |
19913 |
60 |
0 |
0 |
T185 |
117484 |
771 |
0 |
0 |
T186 |
7108 |
21 |
0 |
0 |
T187 |
11385 |
10 |
0 |
0 |
T188 |
63162 |
39 |
0 |
0 |
T190 |
6548 |
9 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
5047 |
0 |
0 |
T116 |
4662 |
16 |
0 |
0 |
T117 |
5037 |
11 |
0 |
0 |
T140 |
108731 |
261 |
0 |
0 |
T159 |
11207 |
37 |
0 |
0 |
T184 |
19913 |
107 |
0 |
0 |
T185 |
117484 |
729 |
0 |
0 |
T186 |
7108 |
2 |
0 |
0 |
T187 |
11385 |
38 |
0 |
0 |
T188 |
63162 |
141 |
0 |
0 |
T190 |
6548 |
17 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4067 |
0 |
0 |
T116 |
4662 |
8 |
0 |
0 |
T117 |
5037 |
20 |
0 |
0 |
T140 |
108731 |
123 |
0 |
0 |
T159 |
11207 |
2 |
0 |
0 |
T184 |
19913 |
84 |
0 |
0 |
T185 |
117484 |
788 |
0 |
0 |
T186 |
7108 |
22 |
0 |
0 |
T187 |
11385 |
21 |
0 |
0 |
T188 |
63162 |
38 |
0 |
0 |
T190 |
6548 |
13 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
5081 |
0 |
0 |
T116 |
4662 |
16 |
0 |
0 |
T117 |
5037 |
12 |
0 |
0 |
T140 |
108731 |
304 |
0 |
0 |
T159 |
11207 |
35 |
0 |
0 |
T184 |
19913 |
69 |
0 |
0 |
T185 |
117484 |
679 |
0 |
0 |
T186 |
7108 |
12 |
0 |
0 |
T187 |
11385 |
13 |
0 |
0 |
T188 |
63162 |
183 |
0 |
0 |
T190 |
6548 |
13 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4431 |
0 |
0 |
T116 |
4662 |
10 |
0 |
0 |
T117 |
5037 |
3 |
0 |
0 |
T140 |
108731 |
177 |
0 |
0 |
T159 |
11207 |
21 |
0 |
0 |
T184 |
19913 |
29 |
0 |
0 |
T185 |
117484 |
738 |
0 |
0 |
T186 |
7108 |
22 |
0 |
0 |
T187 |
11385 |
16 |
0 |
0 |
T188 |
63162 |
42 |
0 |
0 |
T190 |
6548 |
7 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4238 |
0 |
0 |
T116 |
4662 |
10 |
0 |
0 |
T117 |
5037 |
7 |
0 |
0 |
T140 |
108731 |
126 |
0 |
0 |
T159 |
11207 |
25 |
0 |
0 |
T184 |
19913 |
52 |
0 |
0 |
T185 |
117484 |
741 |
0 |
0 |
T186 |
7108 |
42 |
0 |
0 |
T187 |
11385 |
20 |
0 |
0 |
T188 |
63162 |
15 |
0 |
0 |
T190 |
6548 |
9 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4201 |
0 |
0 |
T116 |
4662 |
12 |
0 |
0 |
T117 |
5037 |
13 |
0 |
0 |
T140 |
108731 |
118 |
0 |
0 |
T159 |
11207 |
6 |
0 |
0 |
T184 |
19913 |
55 |
0 |
0 |
T185 |
117484 |
751 |
0 |
0 |
T186 |
7108 |
16 |
0 |
0 |
T187 |
11385 |
14 |
0 |
0 |
T188 |
63162 |
48 |
0 |
0 |
T190 |
6548 |
10 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4196 |
0 |
0 |
T116 |
4662 |
9 |
0 |
0 |
T117 |
5037 |
9 |
0 |
0 |
T140 |
108731 |
93 |
0 |
0 |
T159 |
11207 |
13 |
0 |
0 |
T184 |
19913 |
69 |
0 |
0 |
T185 |
117484 |
779 |
0 |
0 |
T186 |
7108 |
9 |
0 |
0 |
T187 |
11385 |
22 |
0 |
0 |
T188 |
63162 |
44 |
0 |
0 |
T190 |
6548 |
12 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4203 |
0 |
0 |
T116 |
4662 |
11 |
0 |
0 |
T117 |
5037 |
10 |
0 |
0 |
T140 |
108731 |
103 |
0 |
0 |
T159 |
11207 |
8 |
0 |
0 |
T184 |
19913 |
49 |
0 |
0 |
T185 |
117484 |
797 |
0 |
0 |
T186 |
7108 |
18 |
0 |
0 |
T187 |
11385 |
31 |
0 |
0 |
T188 |
63162 |
56 |
0 |
0 |
T190 |
6548 |
10 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4060 |
0 |
0 |
T116 |
4662 |
4 |
0 |
0 |
T117 |
5037 |
6 |
0 |
0 |
T140 |
108731 |
136 |
0 |
0 |
T159 |
11207 |
7 |
0 |
0 |
T184 |
19913 |
61 |
0 |
0 |
T185 |
117484 |
702 |
0 |
0 |
T186 |
7108 |
44 |
0 |
0 |
T187 |
11385 |
17 |
0 |
0 |
T188 |
63162 |
34 |
0 |
0 |
T190 |
6548 |
15 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
434166640 |
4279 |
0 |
0 |
T116 |
4662 |
9 |
0 |
0 |
T117 |
5037 |
12 |
0 |
0 |
T140 |
108731 |
144 |
0 |
0 |
T159 |
11207 |
14 |
0 |
0 |
T184 |
19913 |
62 |
0 |
0 |
T185 |
117484 |
777 |
0 |
0 |
T186 |
7108 |
17 |
0 |
0 |
T187 |
11385 |
19 |
0 |
0 |
T188 |
63162 |
50 |
0 |
0 |
T190 |
6548 |
16 |
0 |
0 |