Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3640191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4432357

1

T2

5

T3

1

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4516878	1			T1	1		T2	1		T3	71
values[0x0]	1776079	1			T2	3		T4	3		T5	58
values[0x1]	1779591	1			T2	4		T5	42		T6	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2598429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5474119

1

T2

5

T3

28

T4

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31149	1			T12	1		T13	5		T15	7
valid_sources[0x01]	33098	1			T6	1		T12	2		T13	3
valid_sources[0x02]	28482	1			T12	3		T13	4		T15	18
valid_sources[0x03]	29725	1			T12	9		T13	5		T15	11
valid_sources[0x04]	32988	1			T12	4		T13	4		T14	13
valid_sources[0x05]	32193	1			T3	1		T12	3		T13	5
valid_sources[0x06]	29327	1			T6	2		T12	4		T15	3
valid_sources[0x07]	36473	1			T3	1		T12	6		T13	5
valid_sources[0x08]	30202	1			T12	1		T13	3		T15	11
valid_sources[0x09]	29825	1			T3	1		T12	11		T13	3
valid_sources[0x0a]	30440	1			T12	2		T13	3		T15	11
valid_sources[0x0b]	29237	1			T13	7		T15	5		T16	4
valid_sources[0x0c]	31705	1			T12	6		T13	6		T15	9
valid_sources[0x0d]	29387	1			T12	4		T13	3		T15	8
valid_sources[0x0e]	31207	1			T8	5		T13	4		T14	2
valid_sources[0x0f]	28202	1			T12	6		T13	2		T15	21
valid_sources[0x10]	31112	1			T3	2		T12	6		T13	6
valid_sources[0x11]	35749	1			T12	11		T13	4		T15	6
valid_sources[0x12]	29930	1			T12	6		T13	2		T15	8
valid_sources[0x13]	32565	1			T12	2		T14	2		T15	11
valid_sources[0x14]	28923	1			T12	7		T13	4		T14	3
valid_sources[0x15]	31592	1			T12	2		T13	2		T15	13
valid_sources[0x16]	40666	1			T12	1		T13	5		T15	13
valid_sources[0x17]	41196	1			T12	6		T13	7		T15	3
valid_sources[0x18]	28797	1			T12	4		T13	5		T15	14
valid_sources[0x19]	30423	1			T12	5		T13	2		T15	9
valid_sources[0x1a]	28670	1			T8	2		T12	3		T13	2
valid_sources[0x1b]	29283	1			T13	10		T15	12		T16	2
valid_sources[0x1c]	31106	1			T12	12		T13	2		T15	21
valid_sources[0x1d]	29692	1			T3	1		T6	1		T12	6
valid_sources[0x1e]	27063	1			T3	3		T12	5		T13	5
valid_sources[0x1f]	31752	1			T3	1		T12	3		T13	3
valid_sources[0x20]	34167	1			T13	3		T15	13		T16	18
valid_sources[0x21]	28860	1			T13	2		T15	4		T16	5
valid_sources[0x22]	43897	1			T12	3		T13	4		T15	14
valid_sources[0x23]	31896	1			T13	3		T15	14		T40	5
valid_sources[0x24]	29617	1			T13	2		T15	12		T16	9
valid_sources[0x25]	29553	1			T12	2		T13	2		T15	12
valid_sources[0x26]	31725	1			T12	8		T13	6		T15	9
valid_sources[0x27]	30739	1			T12	8		T13	3		T14	4
valid_sources[0x28]	34154	1			T3	1		T12	11		T13	7
valid_sources[0x29]	32739	1			T12	5		T13	1		T15	11
valid_sources[0x2a]	50155	1			T13	7		T15	10		T16	12
valid_sources[0x2b]	30629	1			T12	2		T13	3		T15	8
valid_sources[0x2c]	30279	1			T12	5		T13	3		T15	7
valid_sources[0x2d]	34109	1			T12	3		T13	1		T15	11
valid_sources[0x2e]	27737	1			T12	2		T13	6		T15	7
valid_sources[0x2f]	30555	1			T12	9		T13	3		T15	14
valid_sources[0x30]	36723	1			T12	3		T13	5		T15	9
valid_sources[0x31]	40282	1			T12	2		T13	3		T15	4
valid_sources[0x32]	31562	1			T13	4		T14	2		T15	7
valid_sources[0x33]	31477	1			T12	2		T13	5		T15	11
valid_sources[0x34]	34062	1			T12	2		T13	7		T15	7
valid_sources[0x35]	29234	1			T12	3		T13	2		T15	9
valid_sources[0x36]	28253	1			T13	2		T15	21		T16	1
valid_sources[0x37]	30789	1			T12	4		T13	2		T15	14
valid_sources[0x38]	30452	1			T12	1		T13	2		T15	7
valid_sources[0x39]	31667	1			T3	1		T12	6		T14	11
valid_sources[0x3a]	31069	1			T12	4		T13	2		T14	2
valid_sources[0x3b]	32135	1			T12	1		T13	5		T15	7
valid_sources[0x3c]	34642	1			T12	1		T13	3		T15	11
valid_sources[0x3d]	30711	1			T12	1		T13	4		T15	5
valid_sources[0x3e]	29664	1			T3	3		T12	2		T13	1
valid_sources[0x3f]	30227	1			T12	1		T13	1		T15	12
valid_sources[0x40]	31809	1			T12	5		T13	5		T15	8
valid_sources[0x41]	30822	1			T12	6		T13	2		T15	21
valid_sources[0x42]	37306	1			T12	4		T14	1		T15	2
valid_sources[0x43]	28724	1			T13	3		T14	1		T15	9
valid_sources[0x44]	29668	1			T12	4		T13	5		T15	14
valid_sources[0x45]	29961	1			T12	9		T13	5		T15	7
valid_sources[0x46]	28045	1			T12	3		T13	2		T14	1
valid_sources[0x47]	30468	1			T12	5		T13	1		T15	16
valid_sources[0x48]	32216	1			T12	4		T13	4		T15	7
valid_sources[0x49]	31117	1			T8	7		T12	3		T13	2
valid_sources[0x4a]	31602	1			T12	4		T13	2		T15	6
valid_sources[0x4b]	29120	1			T12	2		T13	4		T15	8
valid_sources[0x4c]	33232	1			T12	2		T13	2		T15	10
valid_sources[0x4d]	28392	1			T3	3		T12	2		T13	1
valid_sources[0x4e]	42994	1			T12	5		T13	6		T15	6
valid_sources[0x4f]	31769	1			T3	2		T13	3		T15	1
valid_sources[0x50]	32937	1			T7	1		T8	11		T12	6
valid_sources[0x51]	32006	1			T12	2		T13	1		T14	1
valid_sources[0x52]	31046	1			T6	1		T12	4		T13	1
valid_sources[0x53]	29763	1			T12	11		T13	2		T15	16
valid_sources[0x54]	31499	1			T3	4		T12	9		T13	3
valid_sources[0x55]	30996	1			T12	2		T13	2		T14	13
valid_sources[0x56]	35791	1			T12	7		T13	4		T15	10
valid_sources[0x57]	35783	1			T12	2		T13	5		T15	3
valid_sources[0x58]	33381	1			T12	2		T13	3		T15	7
valid_sources[0x59]	29483	1			T8	4		T12	7		T13	2
valid_sources[0x5a]	29507	1			T12	2		T13	4		T15	7
valid_sources[0x5b]	33280	1			T12	6		T13	4		T15	9
valid_sources[0x5c]	31327	1			T3	2		T12	5		T13	3
valid_sources[0x5d]	30032	1			T12	5		T13	3		T15	10
valid_sources[0x5e]	40032	1			T4	10		T12	4		T13	4
valid_sources[0x5f]	29868	1			T12	3		T13	1		T15	9
valid_sources[0x60]	33350	1			T12	9		T13	2		T15	8
valid_sources[0x61]	31224	1			T6	1		T12	4		T13	5
valid_sources[0x62]	32257	1			T12	3		T13	3		T15	5
valid_sources[0x63]	32445	1			T12	1		T13	2		T15	8
valid_sources[0x64]	30467	1			T8	7		T13	4		T15	6
valid_sources[0x65]	30235	1			T12	9		T13	2		T15	15
valid_sources[0x66]	29570	1			T12	3		T13	1		T15	16
valid_sources[0x67]	30855	1			T12	6		T13	8		T15	12
valid_sources[0x68]	29653	1			T12	6		T13	1		T15	6
valid_sources[0x69]	30538	1			T12	3		T13	3		T15	13
valid_sources[0x6a]	29639	1			T12	3		T13	6		T15	8
valid_sources[0x6b]	29030	1			T3	1		T12	2		T13	4
valid_sources[0x6c]	29783	1			T12	3		T13	2		T15	10
valid_sources[0x6d]	30583	1			T12	4		T13	2		T14	2
valid_sources[0x6e]	30209	1			T3	1		T12	3		T13	5
valid_sources[0x6f]	29820	1			T12	2		T13	4		T15	12
valid_sources[0x70]	30400	1			T12	2		T13	3		T15	13
valid_sources[0x71]	31306	1			T12	2		T13	3		T15	9
valid_sources[0x72]	31337	1			T12	5		T13	3		T15	8
valid_sources[0x73]	30250	1			T3	2		T12	3		T13	1
valid_sources[0x74]	30206	1			T12	2		T13	1		T15	9
valid_sources[0x75]	32134	1			T12	3		T13	4		T15	11
valid_sources[0x76]	31661	1			T12	2		T13	1		T14	2
valid_sources[0x77]	31606	1			T3	1		T12	5		T13	3
valid_sources[0x78]	33430	1			T3	1		T12	1		T13	3
valid_sources[0x79]	36435	1			T12	4		T13	3		T14	2
valid_sources[0x7a]	29531	1			T12	2		T13	7		T15	10
valid_sources[0x7b]	29952	1			T13	1		T15	7		T16	7
valid_sources[0x7c]	29910	1			T8	6		T12	2		T13	3
valid_sources[0x7d]	41399	1			T3	1		T12	4		T13	4
valid_sources[0x7e]	31275	1			T3	1		T12	2		T15	6
valid_sources[0x7f]	31333	1			T12	4		T13	6		T15	8
valid_sources[0x80]	31311	1			T12	1		T13	6		T15	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1202324

1

T2

1

T3

1

T4

1

values[0x0]

all_enables

biggest_size

1625987

1

T2

1

T4

2

T5

58

values[0x1]

all_enables

biggest_size

1604046

1

T2

3

T5

42

T6

2