Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454573226	2991580	0	0
DepthKnown_A	454573226	454436705	0	0
RvalidKnown_A	454573226	454436705	0	0
WreadyKnown_A	454573226	454436705	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	2991580	0	0
T5	1295	100	0	0
T6	768	0	0	0
T7	5383	0	0	0
T8	1429	0	0	0
T9	1808	0	0	0
T10	2655	100	0	0
T11	4854	0	0	0
T12	13559	1669	0	0
T13	76154	1663	0	0
T14	35723	0	0	0
T15	0	1663	0	0
T16	0	1671	0	0
T17	0	1663	0	0
T20	0	832	0	0
T40	0	832	0	0
T41	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454573226	3337582	0	0
DepthKnown_A	454573226	454436705	0	0
RvalidKnown_A	454573226	454436705	0	0
WreadyKnown_A	454573226	454436705	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	3337582	0	0
T5	1295	100	0	0
T6	768	0	0	0
T7	5383	0	0	0
T8	1429	0	0	0
T9	1808	0	0	0
T10	2655	100	0	0
T11	4854	0	0	0
T12	13559	838	0	0
T13	76154	832	0	0
T14	35723	0	0	0
T15	0	832	0	0
T16	0	840	0	0
T17	0	832	0	0
T20	0	832	0	0
T40	0	832	0	0
T41	0	2711	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454573226	202748	0	0
DepthKnown_A	454573226	454436705	0	0
RvalidKnown_A	454573226	454436705	0	0
WreadyKnown_A	454573226	454436705	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	202748	0	0
T4	910	1	0	0
T5	1295	100	0	0
T6	768	0	0	0
T7	5383	0	0	0
T8	1429	0	0	0
T9	1808	0	0	0
T10	2655	100	0	0
T11	4854	33	0	0
T12	13559	0	0	0
T13	76154	0	0	0
T21	0	128	0	0
T28	0	41	0	0
T31	0	283	0	0
T44	0	100	0	0
T45	0	46	0	0
T47	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454573226	485393	0	0
DepthKnown_A	454573226	454436705	0	0
RvalidKnown_A	454573226	454436705	0	0
WreadyKnown_A	454573226	454436705	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	485393	0	0
T4	910	2	0	0
T5	1295	100	0	0
T6	768	0	0	0
T7	5383	0	0	0
T8	1429	0	0	0
T9	1808	0	0	0
T10	2655	100	0	0
T11	4854	33	0	0
T12	13559	0	0	0
T13	76154	0	0	0
T21	0	128	0	0
T28	0	41	0	0
T31	0	283	0	0
T44	0	451	0	0
T45	0	46	0	0
T47	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454573226	6309576	0	0
DepthKnown_A	454573226	454436705	0	0
RvalidKnown_A	454573226	454436705	0	0
WreadyKnown_A	454573226	454436705	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	6309576	0	0
T1	751	1	0	0
T2	1762	8	0	0
T3	1730	71	0	0
T4	910	9	0	0
T5	1295	1	0	0
T6	768	13	0	0
T7	5383	1	0	0
T8	1429	47	0	0
T9	1808	11	0	0
T10	2655	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	454573226	13592643	0	0
DepthKnown_A	454573226	454436705	0	0
RvalidKnown_A	454573226	454436705	0	0
WreadyKnown_A	454573226	454436705	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	13592643	0	0
T1	751	1	0	0
T2	1762	8	0	0
T3	1730	71	0	0
T4	910	35	0	0
T5	1295	1	0	0
T6	768	13	0	0
T7	5383	1	0	0
T8	1429	47	0	0
T9	1808	39	0	0
T10	2655	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454573226	454436705	0	0
T1	751	655	0	0
T2	1762	1680	0	0
T3	1730	1635	0	0
T4	910	839	0	0
T5	1295	1236	0	0
T6	768	716	0	0
T7	5383	3736	0	0
T8	1429	1371	0	0
T9	1808	1729	0	0
T10	2655	2559	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0