Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3623 | 
0 | 
0 | 
| T116 | 
4909 | 
1 | 
0 | 
0 | 
| T117 | 
16242 | 
206 | 
0 | 
0 | 
| T118 | 
17842 | 
245 | 
0 | 
0 | 
| T119 | 
27829 | 
2 | 
0 | 
0 | 
| T120 | 
12292 | 
230 | 
0 | 
0 | 
| T121 | 
13366 | 
217 | 
0 | 
0 | 
| T122 | 
20394 | 
7 | 
0 | 
0 | 
| T131 | 
14472 | 
8 | 
0 | 
0 | 
| T135 | 
3695 | 
5 | 
0 | 
0 | 
| T136 | 
3478 | 
85 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1869 | 
0 | 
0 | 
| T102 | 
2308 | 
2 | 
0 | 
0 | 
| T116 | 
4909 | 
8 | 
0 | 
0 | 
| T131 | 
14472 | 
28 | 
0 | 
0 | 
| T138 | 
10571 | 
17 | 
0 | 
0 | 
| T140 | 
10906 | 
8 | 
0 | 
0 | 
| T149 | 
102653 | 
413 | 
0 | 
0 | 
| T157 | 
13662 | 
22 | 
0 | 
0 | 
| T165 | 
18839 | 
42 | 
0 | 
0 | 
| T166 | 
3989 | 
4 | 
0 | 
0 | 
| T167 | 
7080 | 
8 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1982 | 
0 | 
0 | 
| T102 | 
2308 | 
1 | 
0 | 
0 | 
| T116 | 
4909 | 
6 | 
0 | 
0 | 
| T131 | 
14472 | 
22 | 
0 | 
0 | 
| T138 | 
10571 | 
15 | 
0 | 
0 | 
| T140 | 
10906 | 
5 | 
0 | 
0 | 
| T149 | 
102653 | 
416 | 
0 | 
0 | 
| T157 | 
13662 | 
56 | 
0 | 
0 | 
| T165 | 
18839 | 
50 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
8 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2206 | 
0 | 
0 | 
| T102 | 
2308 | 
8 | 
0 | 
0 | 
| T116 | 
4909 | 
6 | 
0 | 
0 | 
| T131 | 
14472 | 
41 | 
0 | 
0 | 
| T138 | 
10571 | 
14 | 
0 | 
0 | 
| T140 | 
10906 | 
22 | 
0 | 
0 | 
| T149 | 
102653 | 
444 | 
0 | 
0 | 
| T157 | 
13662 | 
41 | 
0 | 
0 | 
| T165 | 
18839 | 
130 | 
0 | 
0 | 
| T166 | 
3989 | 
10 | 
0 | 
0 | 
| T167 | 
7080 | 
15 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
4649 | 
0 | 
0 | 
| T102 | 
2308 | 
4 | 
0 | 
0 | 
| T116 | 
4909 | 
1 | 
0 | 
0 | 
| T131 | 
14472 | 
142 | 
0 | 
0 | 
| T138 | 
10571 | 
133 | 
0 | 
0 | 
| T140 | 
10906 | 
73 | 
0 | 
0 | 
| T149 | 
102653 | 
435 | 
0 | 
0 | 
| T157 | 
13662 | 
49 | 
0 | 
0 | 
| T165 | 
18839 | 
32 | 
0 | 
0 | 
| T166 | 
3989 | 
3 | 
0 | 
0 | 
| T167 | 
7080 | 
85 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
4328 | 
0 | 
0 | 
| T102 | 
2308 | 
1 | 
0 | 
0 | 
| T116 | 
4909 | 
3 | 
0 | 
0 | 
| T131 | 
14472 | 
265 | 
0 | 
0 | 
| T138 | 
10571 | 
9 | 
0 | 
0 | 
| T149 | 
102653 | 
452 | 
0 | 
0 | 
| T157 | 
13662 | 
31 | 
0 | 
0 | 
| T165 | 
18839 | 
77 | 
0 | 
0 | 
| T166 | 
3989 | 
6 | 
0 | 
0 | 
| T167 | 
7080 | 
104 | 
0 | 
0 | 
| T168 | 
18363 | 
31 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
4781 | 
0 | 
0 | 
| T102 | 
2308 | 
1 | 
0 | 
0 | 
| T116 | 
4909 | 
60 | 
0 | 
0 | 
| T131 | 
14472 | 
30 | 
0 | 
0 | 
| T138 | 
10571 | 
138 | 
0 | 
0 | 
| T140 | 
10906 | 
139 | 
0 | 
0 | 
| T149 | 
102653 | 
363 | 
0 | 
0 | 
| T157 | 
13662 | 
17 | 
0 | 
0 | 
| T165 | 
18839 | 
38 | 
0 | 
0 | 
| T166 | 
3989 | 
130 | 
0 | 
0 | 
| T167 | 
7080 | 
142 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
5244 | 
0 | 
0 | 
| T116 | 
4909 | 
4 | 
0 | 
0 | 
| T131 | 
14472 | 
264 | 
0 | 
0 | 
| T138 | 
10571 | 
257 | 
0 | 
0 | 
| T140 | 
10906 | 
175 | 
0 | 
0 | 
| T149 | 
102653 | 
386 | 
0 | 
0 | 
| T157 | 
13662 | 
49 | 
0 | 
0 | 
| T165 | 
18839 | 
71 | 
0 | 
0 | 
| T166 | 
3989 | 
6 | 
0 | 
0 | 
| T167 | 
7080 | 
127 | 
0 | 
0 | 
| T168 | 
18363 | 
20 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
5280 | 
0 | 
0 | 
| T102 | 
2308 | 
2 | 
0 | 
0 | 
| T131 | 
14472 | 
10 | 
0 | 
0 | 
| T138 | 
10571 | 
120 | 
0 | 
0 | 
| T140 | 
10906 | 
128 | 
0 | 
0 | 
| T149 | 
102653 | 
385 | 
0 | 
0 | 
| T157 | 
13662 | 
39 | 
0 | 
0 | 
| T165 | 
18839 | 
47 | 
0 | 
0 | 
| T166 | 
3989 | 
128 | 
0 | 
0 | 
| T167 | 
7080 | 
11 | 
0 | 
0 | 
| T168 | 
18363 | 
32 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
4784 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T116 | 
4909 | 
4 | 
0 | 
0 | 
| T131 | 
14472 | 
129 | 
0 | 
0 | 
| T138 | 
10571 | 
229 | 
0 | 
0 | 
| T140 | 
10906 | 
145 | 
0 | 
0 | 
| T149 | 
102653 | 
430 | 
0 | 
0 | 
| T157 | 
13662 | 
63 | 
0 | 
0 | 
| T165 | 
18839 | 
71 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
9 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
5075 | 
0 | 
0 | 
| T102 | 
2308 | 
8 | 
0 | 
0 | 
| T116 | 
4909 | 
86 | 
0 | 
0 | 
| T131 | 
14472 | 
281 | 
0 | 
0 | 
| T138 | 
10571 | 
269 | 
0 | 
0 | 
| T140 | 
10906 | 
175 | 
0 | 
0 | 
| T149 | 
102653 | 
378 | 
0 | 
0 | 
| T157 | 
13662 | 
26 | 
0 | 
0 | 
| T165 | 
18839 | 
64 | 
0 | 
0 | 
| T166 | 
3989 | 
97 | 
0 | 
0 | 
| T167 | 
7080 | 
112 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
5436 | 
0 | 
0 | 
| T116 | 
4909 | 
71 | 
0 | 
0 | 
| T131 | 
14472 | 
19 | 
0 | 
0 | 
| T138 | 
10571 | 
263 | 
0 | 
0 | 
| T140 | 
10906 | 
90 | 
0 | 
0 | 
| T149 | 
102653 | 
444 | 
0 | 
0 | 
| T157 | 
13662 | 
40 | 
0 | 
0 | 
| T165 | 
18839 | 
112 | 
0 | 
0 | 
| T166 | 
3989 | 
99 | 
0 | 
0 | 
| T167 | 
7080 | 
15 | 
0 | 
0 | 
| T168 | 
18363 | 
43 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3246 | 
0 | 
0 | 
| T102 | 
2308 | 
1 | 
0 | 
0 | 
| T116 | 
4909 | 
18 | 
0 | 
0 | 
| T131 | 
14472 | 
13 | 
0 | 
0 | 
| T138 | 
10571 | 
53 | 
0 | 
0 | 
| T140 | 
10906 | 
18 | 
0 | 
0 | 
| T149 | 
102653 | 
466 | 
0 | 
0 | 
| T157 | 
13662 | 
25 | 
0 | 
0 | 
| T165 | 
18839 | 
46 | 
0 | 
0 | 
| T166 | 
3989 | 
35 | 
0 | 
0 | 
| T167 | 
7080 | 
99 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3279 | 
0 | 
0 | 
| T116 | 
4909 | 
6 | 
0 | 
0 | 
| T131 | 
14472 | 
125 | 
0 | 
0 | 
| T138 | 
10571 | 
79 | 
0 | 
0 | 
| T140 | 
10906 | 
79 | 
0 | 
0 | 
| T149 | 
102653 | 
421 | 
0 | 
0 | 
| T157 | 
13662 | 
49 | 
0 | 
0 | 
| T165 | 
18839 | 
59 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
100 | 
0 | 
0 | 
| T168 | 
18363 | 
59 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3033 | 
0 | 
0 | 
| T102 | 
2308 | 
2 | 
0 | 
0 | 
| T116 | 
4909 | 
28 | 
0 | 
0 | 
| T131 | 
14472 | 
7 | 
0 | 
0 | 
| T138 | 
10571 | 
117 | 
0 | 
0 | 
| T140 | 
10906 | 
20 | 
0 | 
0 | 
| T149 | 
102653 | 
447 | 
0 | 
0 | 
| T157 | 
13662 | 
67 | 
0 | 
0 | 
| T165 | 
18839 | 
84 | 
0 | 
0 | 
| T166 | 
3989 | 
4 | 
0 | 
0 | 
| T167 | 
7080 | 
54 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3090 | 
0 | 
0 | 
| T116 | 
4909 | 
2 | 
0 | 
0 | 
| T131 | 
14472 | 
112 | 
0 | 
0 | 
| T138 | 
10571 | 
157 | 
0 | 
0 | 
| T140 | 
10906 | 
13 | 
0 | 
0 | 
| T149 | 
102653 | 
422 | 
0 | 
0 | 
| T157 | 
13662 | 
90 | 
0 | 
0 | 
| T165 | 
18839 | 
54 | 
0 | 
0 | 
| T166 | 
3989 | 
1 | 
0 | 
0 | 
| T167 | 
7080 | 
107 | 
0 | 
0 | 
| T168 | 
18363 | 
26 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2919 | 
0 | 
0 | 
| T102 | 
2308 | 
6 | 
0 | 
0 | 
| T116 | 
4909 | 
8 | 
0 | 
0 | 
| T131 | 
14472 | 
97 | 
0 | 
0 | 
| T138 | 
10571 | 
100 | 
0 | 
0 | 
| T140 | 
10906 | 
37 | 
0 | 
0 | 
| T149 | 
102653 | 
366 | 
0 | 
0 | 
| T157 | 
13662 | 
17 | 
0 | 
0 | 
| T165 | 
18839 | 
117 | 
0 | 
0 | 
| T166 | 
3989 | 
5 | 
0 | 
0 | 
| T167 | 
7080 | 
40 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2837 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T116 | 
4909 | 
5 | 
0 | 
0 | 
| T131 | 
14472 | 
108 | 
0 | 
0 | 
| T138 | 
10571 | 
17 | 
0 | 
0 | 
| T140 | 
10906 | 
99 | 
0 | 
0 | 
| T149 | 
102653 | 
378 | 
0 | 
0 | 
| T157 | 
13662 | 
52 | 
0 | 
0 | 
| T165 | 
18839 | 
47 | 
0 | 
0 | 
| T166 | 
3989 | 
3 | 
0 | 
0 | 
| T167 | 
7080 | 
127 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3240 | 
0 | 
0 | 
| T102 | 
2308 | 
3 | 
0 | 
0 | 
| T116 | 
4909 | 
19 | 
0 | 
0 | 
| T131 | 
14472 | 
118 | 
0 | 
0 | 
| T138 | 
10571 | 
72 | 
0 | 
0 | 
| T140 | 
10906 | 
55 | 
0 | 
0 | 
| T149 | 
102653 | 
430 | 
0 | 
0 | 
| T157 | 
13662 | 
15 | 
0 | 
0 | 
| T165 | 
18839 | 
52 | 
0 | 
0 | 
| T166 | 
3989 | 
50 | 
0 | 
0 | 
| T167 | 
7080 | 
71 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2882 | 
0 | 
0 | 
| T102 | 
2308 | 
3 | 
0 | 
0 | 
| T116 | 
4909 | 
31 | 
0 | 
0 | 
| T131 | 
14472 | 
85 | 
0 | 
0 | 
| T138 | 
10571 | 
55 | 
0 | 
0 | 
| T140 | 
10906 | 
38 | 
0 | 
0 | 
| T149 | 
102653 | 
462 | 
0 | 
0 | 
| T157 | 
13662 | 
33 | 
0 | 
0 | 
| T165 | 
18839 | 
71 | 
0 | 
0 | 
| T166 | 
3989 | 
7 | 
0 | 
0 | 
| T167 | 
7080 | 
44 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2984 | 
0 | 
0 | 
| T102 | 
2308 | 
3 | 
0 | 
0 | 
| T116 | 
4909 | 
13 | 
0 | 
0 | 
| T131 | 
14472 | 
65 | 
0 | 
0 | 
| T138 | 
10571 | 
90 | 
0 | 
0 | 
| T140 | 
10906 | 
10 | 
0 | 
0 | 
| T149 | 
102653 | 
400 | 
0 | 
0 | 
| T157 | 
13662 | 
24 | 
0 | 
0 | 
| T165 | 
18839 | 
21 | 
0 | 
0 | 
| T166 | 
3989 | 
49 | 
0 | 
0 | 
| T168 | 
18363 | 
53 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3147 | 
0 | 
0 | 
| T102 | 
2308 | 
6 | 
0 | 
0 | 
| T116 | 
4909 | 
55 | 
0 | 
0 | 
| T131 | 
14472 | 
62 | 
0 | 
0 | 
| T138 | 
10571 | 
9 | 
0 | 
0 | 
| T140 | 
10906 | 
50 | 
0 | 
0 | 
| T149 | 
102653 | 
385 | 
0 | 
0 | 
| T157 | 
13662 | 
35 | 
0 | 
0 | 
| T165 | 
18839 | 
66 | 
0 | 
0 | 
| T166 | 
3989 | 
4 | 
0 | 
0 | 
| T167 | 
7080 | 
104 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2787 | 
0 | 
0 | 
| T102 | 
2308 | 
6 | 
0 | 
0 | 
| T116 | 
4909 | 
26 | 
0 | 
0 | 
| T131 | 
14472 | 
84 | 
0 | 
0 | 
| T138 | 
10571 | 
109 | 
0 | 
0 | 
| T140 | 
10906 | 
36 | 
0 | 
0 | 
| T149 | 
102653 | 
384 | 
0 | 
0 | 
| T157 | 
13662 | 
43 | 
0 | 
0 | 
| T165 | 
18839 | 
32 | 
0 | 
0 | 
| T166 | 
3989 | 
1 | 
0 | 
0 | 
| T167 | 
7080 | 
45 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2881 | 
0 | 
0 | 
| T102 | 
2308 | 
9 | 
0 | 
0 | 
| T131 | 
14472 | 
76 | 
0 | 
0 | 
| T138 | 
10571 | 
95 | 
0 | 
0 | 
| T140 | 
10906 | 
80 | 
0 | 
0 | 
| T149 | 
102653 | 
403 | 
0 | 
0 | 
| T157 | 
13662 | 
73 | 
0 | 
0 | 
| T165 | 
18839 | 
49 | 
0 | 
0 | 
| T167 | 
7080 | 
67 | 
0 | 
0 | 
| T168 | 
18363 | 
37 | 
0 | 
0 | 
| T169 | 
14080 | 
61 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2716 | 
0 | 
0 | 
| T116 | 
4909 | 
1 | 
0 | 
0 | 
| T131 | 
14472 | 
124 | 
0 | 
0 | 
| T138 | 
10571 | 
4 | 
0 | 
0 | 
| T140 | 
10906 | 
57 | 
0 | 
0 | 
| T149 | 
102653 | 
387 | 
0 | 
0 | 
| T157 | 
13662 | 
50 | 
0 | 
0 | 
| T165 | 
18839 | 
23 | 
0 | 
0 | 
| T166 | 
3989 | 
39 | 
0 | 
0 | 
| T167 | 
7080 | 
71 | 
0 | 
0 | 
| T168 | 
18363 | 
44 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2974 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T116 | 
4909 | 
6 | 
0 | 
0 | 
| T131 | 
14472 | 
98 | 
0 | 
0 | 
| T138 | 
10571 | 
5 | 
0 | 
0 | 
| T140 | 
10906 | 
20 | 
0 | 
0 | 
| T149 | 
102653 | 
463 | 
0 | 
0 | 
| T157 | 
13662 | 
30 | 
0 | 
0 | 
| T165 | 
18839 | 
94 | 
0 | 
0 | 
| T166 | 
3989 | 
5 | 
0 | 
0 | 
| T167 | 
7080 | 
98 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2977 | 
0 | 
0 | 
| T102 | 
2308 | 
1 | 
0 | 
0 | 
| T116 | 
4909 | 
31 | 
0 | 
0 | 
| T131 | 
14472 | 
115 | 
0 | 
0 | 
| T138 | 
10571 | 
149 | 
0 | 
0 | 
| T140 | 
10906 | 
43 | 
0 | 
0 | 
| T149 | 
102653 | 
422 | 
0 | 
0 | 
| T157 | 
13662 | 
39 | 
0 | 
0 | 
| T165 | 
18839 | 
43 | 
0 | 
0 | 
| T166 | 
3989 | 
5 | 
0 | 
0 | 
| T167 | 
7080 | 
92 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2909 | 
0 | 
0 | 
| T102 | 
2308 | 
2 | 
0 | 
0 | 
| T116 | 
4909 | 
36 | 
0 | 
0 | 
| T131 | 
14472 | 
90 | 
0 | 
0 | 
| T138 | 
10571 | 
11 | 
0 | 
0 | 
| T140 | 
10906 | 
3 | 
0 | 
0 | 
| T149 | 
102653 | 
451 | 
0 | 
0 | 
| T157 | 
13662 | 
46 | 
0 | 
0 | 
| T165 | 
18839 | 
49 | 
0 | 
0 | 
| T166 | 
3989 | 
52 | 
0 | 
0 | 
| T167 | 
7080 | 
12 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2974 | 
0 | 
0 | 
| T102 | 
2308 | 
9 | 
0 | 
0 | 
| T116 | 
4909 | 
4 | 
0 | 
0 | 
| T131 | 
14472 | 
95 | 
0 | 
0 | 
| T138 | 
10571 | 
152 | 
0 | 
0 | 
| T140 | 
10906 | 
59 | 
0 | 
0 | 
| T149 | 
102653 | 
394 | 
0 | 
0 | 
| T157 | 
13662 | 
55 | 
0 | 
0 | 
| T165 | 
18839 | 
70 | 
0 | 
0 | 
| T166 | 
3989 | 
1 | 
0 | 
0 | 
| T167 | 
7080 | 
2 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2717 | 
0 | 
0 | 
| T102 | 
2308 | 
2 | 
0 | 
0 | 
| T116 | 
4909 | 
18 | 
0 | 
0 | 
| T131 | 
14472 | 
21 | 
0 | 
0 | 
| T138 | 
10571 | 
71 | 
0 | 
0 | 
| T140 | 
10906 | 
11 | 
0 | 
0 | 
| T149 | 
102653 | 
371 | 
0 | 
0 | 
| T157 | 
13662 | 
13 | 
0 | 
0 | 
| T165 | 
18839 | 
52 | 
0 | 
0 | 
| T166 | 
3989 | 
1 | 
0 | 
0 | 
| T167 | 
7080 | 
33 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3067 | 
0 | 
0 | 
| T102 | 
2308 | 
6 | 
0 | 
0 | 
| T116 | 
4909 | 
9 | 
0 | 
0 | 
| T131 | 
14472 | 
127 | 
0 | 
0 | 
| T138 | 
10571 | 
121 | 
0 | 
0 | 
| T140 | 
10906 | 
6 | 
0 | 
0 | 
| T149 | 
102653 | 
371 | 
0 | 
0 | 
| T157 | 
13662 | 
92 | 
0 | 
0 | 
| T165 | 
18839 | 
57 | 
0 | 
0 | 
| T166 | 
3989 | 
8 | 
0 | 
0 | 
| T167 | 
7080 | 
40 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2917 | 
0 | 
0 | 
| T116 | 
4909 | 
13 | 
0 | 
0 | 
| T131 | 
14472 | 
77 | 
0 | 
0 | 
| T138 | 
10571 | 
66 | 
0 | 
0 | 
| T140 | 
10906 | 
58 | 
0 | 
0 | 
| T149 | 
102653 | 
367 | 
0 | 
0 | 
| T157 | 
13662 | 
19 | 
0 | 
0 | 
| T165 | 
18839 | 
22 | 
0 | 
0 | 
| T166 | 
3989 | 
49 | 
0 | 
0 | 
| T167 | 
7080 | 
4 | 
0 | 
0 | 
| T168 | 
18363 | 
37 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3159 | 
0 | 
0 | 
| T102 | 
2308 | 
7 | 
0 | 
0 | 
| T116 | 
4909 | 
42 | 
0 | 
0 | 
| T131 | 
14472 | 
70 | 
0 | 
0 | 
| T138 | 
10571 | 
62 | 
0 | 
0 | 
| T140 | 
10906 | 
24 | 
0 | 
0 | 
| T149 | 
102653 | 
442 | 
0 | 
0 | 
| T157 | 
13662 | 
82 | 
0 | 
0 | 
| T165 | 
18839 | 
76 | 
0 | 
0 | 
| T166 | 
3989 | 
5 | 
0 | 
0 | 
| T167 | 
7080 | 
9 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2976 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T131 | 
14472 | 
21 | 
0 | 
0 | 
| T138 | 
10571 | 
75 | 
0 | 
0 | 
| T140 | 
10906 | 
69 | 
0 | 
0 | 
| T149 | 
102653 | 
435 | 
0 | 
0 | 
| T157 | 
13662 | 
25 | 
0 | 
0 | 
| T165 | 
18839 | 
78 | 
0 | 
0 | 
| T166 | 
3989 | 
4 | 
0 | 
0 | 
| T167 | 
7080 | 
60 | 
0 | 
0 | 
| T168 | 
18363 | 
35 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2942 | 
0 | 
0 | 
| T102 | 
2308 | 
4 | 
0 | 
0 | 
| T116 | 
4909 | 
28 | 
0 | 
0 | 
| T131 | 
14472 | 
182 | 
0 | 
0 | 
| T138 | 
10571 | 
104 | 
0 | 
0 | 
| T140 | 
10906 | 
64 | 
0 | 
0 | 
| T149 | 
102653 | 
393 | 
0 | 
0 | 
| T157 | 
13662 | 
59 | 
0 | 
0 | 
| T165 | 
18839 | 
16 | 
0 | 
0 | 
| T166 | 
3989 | 
7 | 
0 | 
0 | 
| T167 | 
7080 | 
10 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3126 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T116 | 
4909 | 
1 | 
0 | 
0 | 
| T131 | 
14472 | 
126 | 
0 | 
0 | 
| T138 | 
10571 | 
117 | 
0 | 
0 | 
| T140 | 
10906 | 
45 | 
0 | 
0 | 
| T149 | 
102653 | 
384 | 
0 | 
0 | 
| T157 | 
13662 | 
49 | 
0 | 
0 | 
| T165 | 
18839 | 
65 | 
0 | 
0 | 
| T166 | 
3989 | 
55 | 
0 | 
0 | 
| T167 | 
7080 | 
66 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1975 | 
0 | 
0 | 
| T102 | 
2308 | 
8 | 
0 | 
0 | 
| T116 | 
4909 | 
6 | 
0 | 
0 | 
| T131 | 
14472 | 
28 | 
0 | 
0 | 
| T138 | 
10571 | 
34 | 
0 | 
0 | 
| T140 | 
10906 | 
4 | 
0 | 
0 | 
| T149 | 
102653 | 
421 | 
0 | 
0 | 
| T157 | 
13662 | 
19 | 
0 | 
0 | 
| T165 | 
18839 | 
64 | 
0 | 
0 | 
| T167 | 
7080 | 
14 | 
0 | 
0 | 
| T168 | 
18363 | 
4 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2023 | 
0 | 
0 | 
| T131 | 
14472 | 
31 | 
0 | 
0 | 
| T138 | 
10571 | 
24 | 
0 | 
0 | 
| T140 | 
10906 | 
11 | 
0 | 
0 | 
| T149 | 
102653 | 
480 | 
0 | 
0 | 
| T157 | 
13662 | 
31 | 
0 | 
0 | 
| T165 | 
18839 | 
48 | 
0 | 
0 | 
| T166 | 
3989 | 
5 | 
0 | 
0 | 
| T167 | 
7080 | 
9 | 
0 | 
0 | 
| T168 | 
18363 | 
48 | 
0 | 
0 | 
| T169 | 
14080 | 
55 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2038 | 
0 | 
0 | 
| T102 | 
2308 | 
3 | 
0 | 
0 | 
| T131 | 
14472 | 
28 | 
0 | 
0 | 
| T138 | 
10571 | 
16 | 
0 | 
0 | 
| T140 | 
10906 | 
11 | 
0 | 
0 | 
| T149 | 
102653 | 
461 | 
0 | 
0 | 
| T157 | 
13662 | 
43 | 
0 | 
0 | 
| T165 | 
18839 | 
53 | 
0 | 
0 | 
| T166 | 
3989 | 
7 | 
0 | 
0 | 
| T167 | 
7080 | 
12 | 
0 | 
0 | 
| T168 | 
18363 | 
11 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2129 | 
0 | 
0 | 
| T102 | 
2308 | 
1 | 
0 | 
0 | 
| T116 | 
4909 | 
7 | 
0 | 
0 | 
| T131 | 
14472 | 
43 | 
0 | 
0 | 
| T138 | 
10571 | 
20 | 
0 | 
0 | 
| T140 | 
10906 | 
9 | 
0 | 
0 | 
| T149 | 
102653 | 
427 | 
0 | 
0 | 
| T157 | 
13662 | 
49 | 
0 | 
0 | 
| T165 | 
18839 | 
104 | 
0 | 
0 | 
| T166 | 
3989 | 
4 | 
0 | 
0 | 
| T167 | 
7080 | 
3 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2226 | 
0 | 
0 | 
| T102 | 
2308 | 
2 | 
0 | 
0 | 
| T116 | 
4909 | 
9 | 
0 | 
0 | 
| T131 | 
14472 | 
21 | 
0 | 
0 | 
| T138 | 
10571 | 
36 | 
0 | 
0 | 
| T140 | 
10906 | 
32 | 
0 | 
0 | 
| T149 | 
102653 | 
414 | 
0 | 
0 | 
| T157 | 
13662 | 
7 | 
0 | 
0 | 
| T165 | 
18839 | 
131 | 
0 | 
0 | 
| T166 | 
3989 | 
3 | 
0 | 
0 | 
| T167 | 
7080 | 
17 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
3513 | 
0 | 
0 | 
| T25 | 
6140 | 
23 | 
0 | 
0 | 
| T31 | 
103007 | 
0 | 
0 | 
0 | 
| T33 | 
5554 | 
0 | 
0 | 
0 | 
| T35 | 
0 | 
13 | 
0 | 
0 | 
| T38 | 
0 | 
32 | 
0 | 
0 | 
| T47 | 
2188 | 
0 | 
0 | 
0 | 
| T50 | 
0 | 
19 | 
0 | 
0 | 
| T53 | 
35628 | 
0 | 
0 | 
0 | 
| T57 | 
19954 | 
0 | 
0 | 
0 | 
| T95 | 
881 | 
0 | 
0 | 
0 | 
| T124 | 
34961 | 
0 | 
0 | 
0 | 
| T129 | 
73285 | 
0 | 
0 | 
0 | 
| T170 | 
0 | 
42 | 
0 | 
0 | 
| T171 | 
0 | 
34 | 
0 | 
0 | 
| T172 | 
0 | 
62 | 
0 | 
0 | 
| T173 | 
0 | 
27 | 
0 | 
0 | 
| T174 | 
0 | 
9 | 
0 | 
0 | 
| T175 | 
0 | 
17 | 
0 | 
0 | 
| T176 | 
1838 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2013 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T116 | 
4909 | 
7 | 
0 | 
0 | 
| T131 | 
14472 | 
17 | 
0 | 
0 | 
| T138 | 
10571 | 
31 | 
0 | 
0 | 
| T140 | 
10906 | 
26 | 
0 | 
0 | 
| T149 | 
102653 | 
404 | 
0 | 
0 | 
| T157 | 
13662 | 
65 | 
0 | 
0 | 
| T165 | 
18839 | 
75 | 
0 | 
0 | 
| T166 | 
3989 | 
6 | 
0 | 
0 | 
| T167 | 
7080 | 
24 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1893 | 
0 | 
0 | 
| T102 | 
2308 | 
2 | 
0 | 
0 | 
| T116 | 
4909 | 
2 | 
0 | 
0 | 
| T131 | 
14472 | 
19 | 
0 | 
0 | 
| T138 | 
10571 | 
38 | 
0 | 
0 | 
| T140 | 
10906 | 
14 | 
0 | 
0 | 
| T149 | 
102653 | 
412 | 
0 | 
0 | 
| T157 | 
13662 | 
23 | 
0 | 
0 | 
| T165 | 
18839 | 
60 | 
0 | 
0 | 
| T167 | 
7080 | 
9 | 
0 | 
0 | 
| T168 | 
18363 | 
35 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1900 | 
0 | 
0 | 
| T102 | 
2308 | 
9 | 
0 | 
0 | 
| T116 | 
4909 | 
5 | 
0 | 
0 | 
| T131 | 
14472 | 
26 | 
0 | 
0 | 
| T138 | 
10571 | 
18 | 
0 | 
0 | 
| T149 | 
102653 | 
391 | 
0 | 
0 | 
| T157 | 
13662 | 
10 | 
0 | 
0 | 
| T165 | 
18839 | 
37 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
7 | 
0 | 
0 | 
| T168 | 
18363 | 
39 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1920 | 
0 | 
0 | 
| T102 | 
2308 | 
2 | 
0 | 
0 | 
| T116 | 
4909 | 
1 | 
0 | 
0 | 
| T131 | 
14472 | 
14 | 
0 | 
0 | 
| T138 | 
10571 | 
22 | 
0 | 
0 | 
| T140 | 
10906 | 
1 | 
0 | 
0 | 
| T149 | 
102653 | 
395 | 
0 | 
0 | 
| T157 | 
13662 | 
52 | 
0 | 
0 | 
| T165 | 
18839 | 
92 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
6 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1902 | 
0 | 
0 | 
| T131 | 
14472 | 
26 | 
0 | 
0 | 
| T138 | 
10571 | 
5 | 
0 | 
0 | 
| T140 | 
10906 | 
9 | 
0 | 
0 | 
| T149 | 
102653 | 
440 | 
0 | 
0 | 
| T157 | 
13662 | 
81 | 
0 | 
0 | 
| T165 | 
18839 | 
99 | 
0 | 
0 | 
| T166 | 
3989 | 
9 | 
0 | 
0 | 
| T167 | 
7080 | 
3 | 
0 | 
0 | 
| T168 | 
18363 | 
8 | 
0 | 
0 | 
| T169 | 
14080 | 
20 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1857 | 
0 | 
0 | 
| T102 | 
2308 | 
9 | 
0 | 
0 | 
| T116 | 
4909 | 
6 | 
0 | 
0 | 
| T131 | 
14472 | 
22 | 
0 | 
0 | 
| T138 | 
10571 | 
11 | 
0 | 
0 | 
| T140 | 
10906 | 
15 | 
0 | 
0 | 
| T149 | 
102653 | 
419 | 
0 | 
0 | 
| T157 | 
13662 | 
25 | 
0 | 
0 | 
| T165 | 
18839 | 
72 | 
0 | 
0 | 
| T166 | 
3989 | 
8 | 
0 | 
0 | 
| T167 | 
7080 | 
4 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2101 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T116 | 
4909 | 
8 | 
0 | 
0 | 
| T131 | 
14472 | 
22 | 
0 | 
0 | 
| T138 | 
10571 | 
27 | 
0 | 
0 | 
| T140 | 
10906 | 
27 | 
0 | 
0 | 
| T149 | 
102653 | 
415 | 
0 | 
0 | 
| T157 | 
13662 | 
63 | 
0 | 
0 | 
| T165 | 
18839 | 
73 | 
0 | 
0 | 
| T166 | 
3989 | 
1 | 
0 | 
0 | 
| T167 | 
7080 | 
10 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1894 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T116 | 
4909 | 
6 | 
0 | 
0 | 
| T131 | 
14472 | 
24 | 
0 | 
0 | 
| T138 | 
10571 | 
14 | 
0 | 
0 | 
| T140 | 
10906 | 
8 | 
0 | 
0 | 
| T149 | 
102653 | 
481 | 
0 | 
0 | 
| T157 | 
13662 | 
21 | 
0 | 
0 | 
| T165 | 
18839 | 
53 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
4 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
2441 | 
0 | 
0 | 
| T116 | 
4909 | 
19 | 
0 | 
0 | 
| T131 | 
14472 | 
47 | 
0 | 
0 | 
| T138 | 
10571 | 
43 | 
0 | 
0 | 
| T140 | 
10906 | 
5 | 
0 | 
0 | 
| T149 | 
102653 | 
417 | 
0 | 
0 | 
| T157 | 
13662 | 
84 | 
0 | 
0 | 
| T165 | 
18839 | 
105 | 
0 | 
0 | 
| T166 | 
3989 | 
6 | 
0 | 
0 | 
| T167 | 
7080 | 
17 | 
0 | 
0 | 
| T168 | 
18363 | 
27 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1959 | 
0 | 
0 | 
| T102 | 
2308 | 
5 | 
0 | 
0 | 
| T131 | 
14472 | 
18 | 
0 | 
0 | 
| T138 | 
10571 | 
6 | 
0 | 
0 | 
| T140 | 
10906 | 
2 | 
0 | 
0 | 
| T149 | 
102653 | 
444 | 
0 | 
0 | 
| T157 | 
13662 | 
29 | 
0 | 
0 | 
| T165 | 
18839 | 
70 | 
0 | 
0 | 
| T167 | 
7080 | 
10 | 
0 | 
0 | 
| T168 | 
18363 | 
4 | 
0 | 
0 | 
| T169 | 
14080 | 
67 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1868 | 
0 | 
0 | 
| T102 | 
2308 | 
6 | 
0 | 
0 | 
| T116 | 
4909 | 
7 | 
0 | 
0 | 
| T131 | 
14472 | 
19 | 
0 | 
0 | 
| T138 | 
10571 | 
8 | 
0 | 
0 | 
| T149 | 
102653 | 
420 | 
0 | 
0 | 
| T157 | 
13662 | 
33 | 
0 | 
0 | 
| T165 | 
18839 | 
51 | 
0 | 
0 | 
| T166 | 
3989 | 
3 | 
0 | 
0 | 
| T167 | 
7080 | 
3 | 
0 | 
0 | 
| T168 | 
18363 | 
12 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1950 | 
0 | 
0 | 
| T102 | 
2308 | 
1 | 
0 | 
0 | 
| T116 | 
4909 | 
6 | 
0 | 
0 | 
| T131 | 
14472 | 
25 | 
0 | 
0 | 
| T138 | 
10571 | 
9 | 
0 | 
0 | 
| T140 | 
10906 | 
1 | 
0 | 
0 | 
| T149 | 
102653 | 
469 | 
0 | 
0 | 
| T157 | 
13662 | 
21 | 
0 | 
0 | 
| T165 | 
18839 | 
62 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
12 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1860 | 
0 | 
0 | 
| T102 | 
2308 | 
1 | 
0 | 
0 | 
| T116 | 
4909 | 
4 | 
0 | 
0 | 
| T131 | 
14472 | 
23 | 
0 | 
0 | 
| T138 | 
10571 | 
5 | 
0 | 
0 | 
| T140 | 
10906 | 
9 | 
0 | 
0 | 
| T149 | 
102653 | 
428 | 
0 | 
0 | 
| T157 | 
13662 | 
27 | 
0 | 
0 | 
| T165 | 
18839 | 
80 | 
0 | 
0 | 
| T167 | 
7080 | 
4 | 
0 | 
0 | 
| T168 | 
18363 | 
31 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1878 | 
0 | 
0 | 
| T102 | 
2308 | 
4 | 
0 | 
0 | 
| T116 | 
4909 | 
8 | 
0 | 
0 | 
| T131 | 
14472 | 
26 | 
0 | 
0 | 
| T138 | 
10571 | 
7 | 
0 | 
0 | 
| T140 | 
10906 | 
3 | 
0 | 
0 | 
| T149 | 
102653 | 
446 | 
0 | 
0 | 
| T157 | 
13662 | 
14 | 
0 | 
0 | 
| T165 | 
18839 | 
110 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
8 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1841 | 
0 | 
0 | 
| T102 | 
2308 | 
4 | 
0 | 
0 | 
| T116 | 
4909 | 
5 | 
0 | 
0 | 
| T131 | 
14472 | 
10 | 
0 | 
0 | 
| T138 | 
10571 | 
15 | 
0 | 
0 | 
| T140 | 
10906 | 
2 | 
0 | 
0 | 
| T149 | 
102653 | 
468 | 
0 | 
0 | 
| T157 | 
13662 | 
12 | 
0 | 
0 | 
| T165 | 
18839 | 
47 | 
0 | 
0 | 
| T166 | 
3989 | 
2 | 
0 | 
0 | 
| T167 | 
7080 | 
6 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
454573226 | 
1777 | 
0 | 
0 | 
| T102 | 
2308 | 
3 | 
0 | 
0 | 
| T131 | 
14472 | 
26 | 
0 | 
0 | 
| T138 | 
10571 | 
16 | 
0 | 
0 | 
| T140 | 
10906 | 
10 | 
0 | 
0 | 
| T149 | 
102653 | 
447 | 
0 | 
0 | 
| T157 | 
13662 | 
47 | 
0 | 
0 | 
| T165 | 
18839 | 
53 | 
0 | 
0 | 
| T166 | 
3989 | 
4 | 
0 | 
0 | 
| T167 | 
7080 | 
8 | 
0 | 
0 | 
| T168 | 
18363 | 
53 | 
0 | 
0 |