Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3874274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4323439

1

T1

7

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4670687	1			T1	1		T2	51		T3	1
values[0x0]	1762694	1			T1	3		T4	37		T5	3
values[0x1]	1764332	1			T1	6		T4	63		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2752608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5445105

1

T1

7

T2

24

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30749	1			T7	1		T26	2		T13	2
valid_sources[0x01]	30665	1			T26	1		T11	1		T14	5
valid_sources[0x02]	29449	1			T14	3		T15	3		T16	6
valid_sources[0x03]	33220	1			T8	1		T26	2		T14	1
valid_sources[0x04]	28720	1			T4	1		T6	4		T13	14
valid_sources[0x05]	29583	1			T4	2		T6	7		T11	1
valid_sources[0x06]	28905	1			T7	2		T10	2		T26	1
valid_sources[0x07]	30013	1			T6	13		T26	1		T11	3
valid_sources[0x08]	30867	1			T4	2		T26	2		T11	1
valid_sources[0x09]	31108	1			T4	2		T13	7		T14	8
valid_sources[0x0a]	29309	1			T4	1		T9	1		T26	1
valid_sources[0x0b]	34700	1			T4	1		T26	1		T13	5
valid_sources[0x0c]	30461	1			T4	1		T26	1		T14	3
valid_sources[0x0d]	29027	1			T4	1		T5	1		T26	1
valid_sources[0x0e]	35019	1			T4	6		T6	1		T7	1
valid_sources[0x0f]	32845	1			T26	1		T11	2		T14	3
valid_sources[0x10]	34270	1			T4	2		T8	2		T13	3
valid_sources[0x11]	32654	1			T4	4		T15	9		T16	8
valid_sources[0x12]	29843	1			T10	3		T13	8		T14	9
valid_sources[0x13]	29558	1			T4	1		T13	6		T15	6
valid_sources[0x14]	30066	1			T4	1		T6	1		T8	2
valid_sources[0x15]	31371	1			T4	1		T7	2		T26	1
valid_sources[0x16]	31567	1			T6	10		T26	1		T13	4
valid_sources[0x17]	30455	1			T4	4		T8	1		T13	3
valid_sources[0x18]	32685	1			T4	1		T15	2		T16	1
valid_sources[0x19]	30452	1			T9	1		T26	1		T14	3
valid_sources[0x1a]	31036	1			T6	1		T7	10		T13	3
valid_sources[0x1b]	31030	1			T6	3		T7	4		T26	2
valid_sources[0x1c]	29313	1			T6	8		T26	1		T11	2
valid_sources[0x1d]	28713	1			T13	10		T14	9		T15	3
valid_sources[0x1e]	30940	1			T13	8		T14	4		T15	4
valid_sources[0x1f]	29269	1			T4	1		T8	1		T11	1
valid_sources[0x20]	28765	1			T4	1		T26	1		T11	3
valid_sources[0x21]	32173	1			T26	1		T14	4		T15	3
valid_sources[0x22]	29820	1			T9	2		T13	5		T14	4
valid_sources[0x23]	30525	1			T4	1		T8	2		T26	1
valid_sources[0x24]	30318	1			T4	3		T7	15		T8	1
valid_sources[0x25]	31668	1			T4	2		T26	2		T11	5
valid_sources[0x26]	31497	1			T4	2		T6	4		T26	1
valid_sources[0x27]	27561	1			T7	5		T26	2		T14	3
valid_sources[0x28]	33578	1			T6	1		T26	1		T11	1
valid_sources[0x29]	29526	1			T8	1		T11	4		T14	2
valid_sources[0x2a]	31714	1			T4	1		T26	1		T13	8
valid_sources[0x2b]	30911	1			T6	8		T11	1		T13	7
valid_sources[0x2c]	32032	1			T6	3		T8	1		T26	2
valid_sources[0x2d]	36260	1			T4	2		T7	3		T8	1
valid_sources[0x2e]	28622	1			T7	2		T26	1		T11	1
valid_sources[0x2f]	30281	1			T4	1		T7	2		T13	3
valid_sources[0x30]	30296	1			T6	2		T13	2		T14	3
valid_sources[0x31]	30370	1			T4	1		T6	5		T7	15
valid_sources[0x32]	31449	1			T4	1		T6	2		T8	1
valid_sources[0x33]	32909	1			T6	10		T7	1		T26	1
valid_sources[0x34]	31060	1			T4	1		T6	5		T26	2
valid_sources[0x35]	32109	1			T4	2		T6	11		T7	1
valid_sources[0x36]	30933	1			T4	1		T14	4		T15	1
valid_sources[0x37]	29584	1			T6	1		T11	2		T14	3
valid_sources[0x38]	31837	1			T4	1		T13	4		T14	4
valid_sources[0x39]	28886	1			T3	1		T26	2		T14	5
valid_sources[0x3a]	31588	1			T6	4		T13	2		T14	8
valid_sources[0x3b]	31150	1			T4	2		T7	10		T26	1
valid_sources[0x3c]	30021	1			T26	1		T13	3		T14	1
valid_sources[0x3d]	27883	1			T4	1		T7	1		T8	1
valid_sources[0x3e]	28901	1			T4	1		T6	4		T7	3
valid_sources[0x3f]	32322	1			T9	3		T26	1		T13	2
valid_sources[0x40]	29747	1			T6	2		T14	4		T16	3
valid_sources[0x41]	29946	1			T4	2		T7	4		T26	1
valid_sources[0x42]	34001	1			T14	1		T15	6		T16	3
valid_sources[0x43]	32467	1			T6	8		T8	2		T13	4
valid_sources[0x44]	29585	1			T4	1		T15	5		T21	4
valid_sources[0x45]	35321	1			T4	1		T6	10		T26	3
valid_sources[0x46]	34600	1			T8	1		T26	1		T11	2
valid_sources[0x47]	32899	1			T7	14		T11	2		T14	1
valid_sources[0x48]	31289	1			T7	11		T11	2		T13	8
valid_sources[0x49]	31920	1			T4	1		T6	22		T8	1
valid_sources[0x4a]	31808	1			T6	2		T7	1		T26	1
valid_sources[0x4b]	32987	1			T5	2		T6	12		T13	10
valid_sources[0x4c]	32276	1			T7	8		T15	2		T16	10
valid_sources[0x4d]	28812	1			T4	1		T26	1		T11	1
valid_sources[0x4e]	32346	1			T7	9		T26	2		T11	1
valid_sources[0x4f]	31450	1			T7	5		T26	1		T11	1
valid_sources[0x50]	30949	1			T6	5		T7	7		T26	1
valid_sources[0x51]	31563	1			T4	1		T7	5		T11	3
valid_sources[0x52]	30377	1			T7	3		T8	1		T13	8
valid_sources[0x53]	28606	1			T4	2		T13	9		T14	5
valid_sources[0x54]	28894	1			T7	2		T9	1		T26	1
valid_sources[0x55]	30420	1			T11	2		T13	34		T14	3
valid_sources[0x56]	30159	1			T4	1		T6	13		T9	2
valid_sources[0x57]	33606	1			T7	3		T13	28		T14	5
valid_sources[0x58]	31518	1			T4	1		T13	2		T15	9
valid_sources[0x59]	28199	1			T4	3		T6	4		T26	1
valid_sources[0x5a]	43439	1			T6	13		T26	1		T14	3
valid_sources[0x5b]	37266	1			T4	2		T13	9		T14	4
valid_sources[0x5c]	29272	1			T4	1		T6	6		T26	1
valid_sources[0x5d]	30027	1			T4	1		T10	2		T11	1
valid_sources[0x5e]	34401	1			T11	1		T13	11		T14	8
valid_sources[0x5f]	30703	1			T5	2		T14	2		T15	6
valid_sources[0x60]	31559	1			T4	1		T26	1		T14	5
valid_sources[0x61]	30839	1			T4	2		T7	2		T8	1
valid_sources[0x62]	100127	1			T4	1		T7	4		T26	1
valid_sources[0x63]	30069	1			T4	1		T7	11		T26	1
valid_sources[0x64]	33768	1			T4	1		T26	1		T13	3
valid_sources[0x65]	30618	1			T4	1		T26	2		T13	3
valid_sources[0x66]	31800	1			T4	1		T7	1		T26	1
valid_sources[0x67]	27515	1			T4	4		T6	31		T26	2
valid_sources[0x68]	30210	1			T26	1		T11	3		T13	10
valid_sources[0x69]	30813	1			T4	3		T10	9		T26	1
valid_sources[0x6a]	31805	1			T4	1		T6	1		T26	3
valid_sources[0x6b]	39166	1			T4	3		T7	3		T26	1
valid_sources[0x6c]	37623	1			T10	3		T26	3		T14	5
valid_sources[0x6d]	30173	1			T4	1		T6	1		T13	2
valid_sources[0x6e]	29245	1			T4	1		T26	1		T11	1
valid_sources[0x6f]	28402	1			T4	1		T11	2		T14	7
valid_sources[0x70]	30341	1			T11	1		T13	6		T14	3
valid_sources[0x71]	33014	1			T4	2		T14	2		T15	3
valid_sources[0x72]	30483	1			T4	1		T6	8		T8	1
valid_sources[0x73]	35615	1			T6	3		T13	15		T14	5
valid_sources[0x74]	29397	1			T14	6		T15	1		T16	6
valid_sources[0x75]	31157	1			T6	21		T13	12		T14	9
valid_sources[0x76]	30620	1			T4	1		T6	6		T7	1
valid_sources[0x77]	29236	1			T4	1		T7	3		T8	2
valid_sources[0x78]	31326	1			T6	3		T7	1		T26	1
valid_sources[0x79]	32136	1			T26	3		T13	2		T14	5
valid_sources[0x7a]	30976	1			T4	1		T26	1		T14	2
valid_sources[0x7b]	29867	1			T4	1		T7	4		T26	1
valid_sources[0x7c]	29223	1			T13	18		T14	2		T15	1
valid_sources[0x7d]	31204	1			T4	1		T26	2		T11	5
valid_sources[0x7e]	34050	1			T14	1		T15	3		T16	4
valid_sources[0x7f]	30591	1			T4	1		T13	3		T14	3
valid_sources[0x80]	28754	1			T6	6		T26	1		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1147264

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1600333

1

T1

2

T4

37

T5

2

values[0x1]

all_enables

biggest_size

1575842

1

T1

4

T4

63

T5

3