Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3897593

1

T1

3

T2

50

T5

2

full_word

4322758

1

T1

7

T2

1

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8220001	1			T1	10		T2	51		T3	1
auto[TlIntgErrCmd]	94	1			T127	1		T128	4		T140	3
auto[TlIntgErrData]	131	1			T127	4		T128	4		T129	7
auto[TlIntgErrBoth]	125	1			T127	5		T128	2		T129	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4674174

1

T1

1

T2

51

T3

1

auto[1]

3546177

1

T1

9

T5

7

T6

268

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3526504	1			T2	50		T6	174		T7	305
auto[TlIntgErrNone]	partial	auto[1]	370770	1			T1	3		T5	2		T6	121
auto[TlIntgErrNone]	full_word	auto[0]	1147513	1			T1	1		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3175214	1			T1	6		T5	5		T6	147
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T128	2		T140	1		T215	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T127	1		T128	1		T140	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T128	1		T216	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T213	1		T217	1		T218	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T127	1		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[1]	70	1			T127	3		T128	3		T129	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T129	2		T219	2		T212	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T129	1		T213	1		T214	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T127	1		T128	1		T140	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T127	2		T128	1		T129	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T127	2		T219	1		T211	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T129	1		T140	2		T213	1