Unified Coverage Report :: Module :: prim_generic_ram_2p

Module : prim_generic_ram_2p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_ram_2p

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	91	6	6	100.00

48                        logic unused_cfg;
49         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T3 
50                      
51                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
52                        // to be the full bit mask.
53                        localparam int MaskWidth = Width / DataBitsPerMask;
54                      
55                        logic [Width-1:0]     mem [Depth];
56                        logic [MaskWidth-1:0] a_wmask;
57                        logic [MaskWidth-1:0] b_wmask;
58                      
59                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
60         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
61         4/4              assign b_wmask[k] = &b_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
62                      
63                          // Ensure that all mask bits within a group have the same value for a write
64                          `ASSERT(MaskCheckPortA_A, a_req_i && a_write_i |->
65                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
66                              clk_a_i, '0)
67                          `ASSERT(MaskCheckPortB_A, b_req_i && b_write_i |->
68                              b_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
69                              clk_b_i, '0)
70                        end
71                      
72                        // Xilinx FPGA specific Dual-port RAM coding style
73                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
74                        // thrown due to 'mem' being driven by two always processes below
75                        always @(posedge clk_a_i) begin
76         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
77         1/1                if (a_write_i) begin
           Tests:       T4 T6 T7 
78         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T4 T6 T7 
79         1/1                    if (a_wmask[i]) begin
           Tests:       T4 T6 T7 
80         1/1                      mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T4 T6 T7 
81                                    a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
82                                end
                   ==>  MISSING_ELSE
83                              end
84                            end else begin
85         1/1                  a_rdata_o <= mem[a_addr_i];
           Tests:       T4 T6 T26 
86                            end
87                          end
                        MISSING_ELSE
88                        end
89                      
90                        always @(posedge clk_b_i) begin
91         1/1              if (b_req_i) begin
           Tests:       T5 T6 T7 
92         1/1                if (b_write_i) begin
           Tests:       T6 T7 T11 
93         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T6 T11 T28 
94         1/1                    if (b_wmask[i]) begin
           Tests:       T6 T11 T28 
95         1/1                      mem[b_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T6 T11 T28 
96                                    b_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
97                                end
                        MISSING_ELSE
98                              end
99                            end else begin
100        1/1                  b_rdata_o <= mem[b_addr_i];
           Tests:       T6 T7 T11 
101                           end
102                         end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_2p

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	76	3	3	100.00
IF	91	3	3	100.00

76             if (a_req_i) begin
               -1-  
77               if (a_write_i) begin
                 -2-  
78                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
79                   if (a_wmask[i]) begin
80                     mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
81                       a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
82                   end
83                 end
84               end else begin
85                 a_rdata_o <= mem[a_addr_i];
                   ==>
86               end
87             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T26
0	-	Covered	T1,T2,T3

91             if (b_req_i) begin
               -1-  
92               if (b_write_i) begin
                 -2-  
93                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
94                   if (b_wmask[i]) begin
95                     mem[b_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
96                       b_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
97                   end
98                 end
99               end else begin
100                b_rdata_o <= mem[b_addr_i];
                   ==>
101              end
102            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T6,T11,T28
1	0	Covered	T6,T7,T11
0	-	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_generic_ram_2p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	454850675	1995826	0	0
gen_wmask[0].MaskCheckPortB_A	140189703	1248184	0	0
gen_wmask[1].MaskCheckPortA_A	454850675	1995826	0	0
gen_wmask[1].MaskCheckPortB_A	140189703	1248184	0	0
gen_wmask[2].MaskCheckPortA_A	454850675	1995826	0	0
gen_wmask[2].MaskCheckPortB_A	140189703	1248184	0	0
gen_wmask[3].MaskCheckPortA_A	454850675	1995826	0	0
gen_wmask[3].MaskCheckPortB_A	140189703	1248184	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454850675	1995826	0	0
T4	1191	100	0	0
T5	1690	0	0	0
T6	12330	75	0	0
T7	2296	6	0	0
T8	1110	0	0	0
T9	796	0	0	0
T10	6795	0	0	0
T11	1398	12	0	0
T12	7611	0	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T26	2327	100	0	0

gen_wmask[0].MaskCheckPortB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140189703	1248184	0	0
T6	29446	444	0	0
T7	432	0	0	0
T10	762	0	0	0
T11	1240	68	0	0
T13	1362	0	0	0
T14	12966	0	0	0
T15	56310	0	0	0
T16	29086	0	0	0
T17	45084	0	0	0
T19	16479	0	0	0
T24	0	520	0	0
T28	0	186	0	0
T31	0	260	0	0
T45	0	1910	0	0
T46	0	1861	0	0
T48	0	136	0	0
T56	0	4	0	0
T80	0	4283	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454850675	1995826	0	0
T4	1191	100	0	0
T5	1690	0	0	0
T6	12330	75	0	0
T7	2296	6	0	0
T8	1110	0	0	0
T9	796	0	0	0
T10	6795	0	0	0
T11	1398	12	0	0
T12	7611	0	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T26	2327	100	0	0

gen_wmask[1].MaskCheckPortB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140189703	1248184	0	0
T6	29446	444	0	0
T7	432	0	0	0
T10	762	0	0	0
T11	1240	68	0	0
T13	1362	0	0	0
T14	12966	0	0	0
T15	56310	0	0	0
T16	29086	0	0	0
T17	45084	0	0	0
T19	16479	0	0	0
T24	0	520	0	0
T28	0	186	0	0
T31	0	260	0	0
T45	0	1910	0	0
T46	0	1861	0	0
T48	0	136	0	0
T56	0	4	0	0
T80	0	4283	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454850675	1995826	0	0
T4	1191	100	0	0
T5	1690	0	0	0
T6	12330	75	0	0
T7	2296	6	0	0
T8	1110	0	0	0
T9	796	0	0	0
T10	6795	0	0	0
T11	1398	12	0	0
T12	7611	0	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T26	2327	100	0	0

gen_wmask[2].MaskCheckPortB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140189703	1248184	0	0
T6	29446	444	0	0
T7	432	0	0	0
T10	762	0	0	0
T11	1240	68	0	0
T13	1362	0	0	0
T14	12966	0	0	0
T15	56310	0	0	0
T16	29086	0	0	0
T17	45084	0	0	0
T19	16479	0	0	0
T24	0	520	0	0
T28	0	186	0	0
T31	0	260	0	0
T45	0	1910	0	0
T46	0	1861	0	0
T48	0	136	0	0
T56	0	4	0	0
T80	0	4283	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454850675	1995826	0	0
T4	1191	100	0	0
T5	1690	0	0	0
T6	12330	75	0	0
T7	2296	6	0	0
T8	1110	0	0	0
T9	796	0	0	0
T10	6795	0	0	0
T11	1398	12	0	0
T12	7611	0	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T26	2327	100	0	0

gen_wmask[3].MaskCheckPortB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140189703	1248184	0	0
T6	29446	444	0	0
T7	432	0	0	0
T10	762	0	0	0
T11	1240	68	0	0
T13	1362	0	0	0
T14	12966	0	0	0
T15	56310	0	0	0
T16	29086	0	0	0
T17	45084	0	0	0
T19	16479	0	0	0
T24	0	520	0	0
T28	0	186	0	0
T31	0	260	0	0
T45	0	1910	0	0
T46	0	1861	0	0
T48	0	136	0	0
T56	0	4	0	0
T80	0	4283	0	0