Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457361206	2745351	0	0
DataKnown_AKnownEnable	457361206	457233476	0	0
DepthKnown_A	457361206	457233476	0	0
RvalidKnown_A	457361206	457233476	0	0
WreadyKnown_A	457361206	457233476	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	2745351	0	0
T4	1191	100	0	0
T5	1690	0	0	0
T6	12330	0	0	0
T7	2296	0	0	0
T8	1110	0	0	0
T9	796	0	0	0
T10	6795	0	0	0
T11	1398	0	0	0
T12	7611	0	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	1663	0	0
T19	0	1663	0	0
T21	0	832	0	0
T26	2327	100	0	0
T44	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457361206	2908851	0	0
DataKnown_AKnownEnable	457361206	457233476	0	0
DepthKnown_A	457361206	457233476	0	0
RvalidKnown_A	457361206	457233476	0	0
WreadyKnown_A	457361206	457233476	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	2908851	0	0
T4	1191	100	0	0
T5	1690	0	0	0
T6	12330	0	0	0
T7	2296	0	0	0
T8	1110	0	0	0
T9	796	0	0	0
T10	6795	0	0	0
T11	1398	0	0	0
T12	7611	0	0	0
T13	0	832	0	0
T14	0	2499	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T19	0	832	0	0
T21	0	3702	0	0
T26	2327	100	0	0
T44	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457361206	194886	0	0
DataKnown_AKnownEnable	457361206	457233476	0	0
DepthKnown_A	457361206	457233476	0	0
RvalidKnown_A	457361206	457233476	0	0
WreadyKnown_A	457361206	457233476	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	194886	0	0
T4	1191	100	0	0
T5	1690	0	0	0
T6	12330	115	0	0
T7	2296	0	0	0
T8	1110	0	0	0
T9	796	0	0	0
T10	6795	0	0	0
T11	1398	17	0	0
T12	7611	0	0	0
T24	0	128	0	0
T26	2327	100	0	0
T28	0	47	0	0
T31	0	66	0	0
T44	0	100	0	0
T47	0	100	0	0
T48	0	35	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457361206	421997	0	0
DataKnown_AKnownEnable	457361206	457233476	0	0
DepthKnown_A	457361206	457233476	0	0
RvalidKnown_A	457361206	457233476	0	0
WreadyKnown_A	457361206	457233476	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	421997	0	0
T4	1191	100	0	0
T5	1690	0	0	0
T6	12330	505	0	0
T7	2296	0	0	0
T8	1110	0	0	0
T9	796	0	0	0
T10	6795	0	0	0
T11	1398	17	0	0
T12	7611	0	0	0
T24	0	128	0	0
T26	2327	100	0	0
T28	0	47	0	0
T31	0	320	0	0
T44	0	100	0	0
T47	0	479	0	0
T48	0	154	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457361206	6545301	0	0
DataKnown_AKnownEnable	457361206	457233476	0	0
DepthKnown_A	457361206	457233476	0	0
RvalidKnown_A	457361206	457233476	0	0
WreadyKnown_A	457361206	457233476	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	6545301	0	0
T1	1363	10	0	0
T2	1816	51	0	0
T3	1550	1	0	0
T4	1191	1	0	0
T5	1690	8	0	0
T6	12330	526	0	0
T7	2296	322	0	0
T8	1110	47	0	0
T9	796	15	0	0
T10	6795	29	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457361206	11867824	0	0
DataKnown_AKnownEnable	457361206	457233476	0	0
DepthKnown_A	457361206	457233476	0	0
RvalidKnown_A	457361206	457233476	0	0
WreadyKnown_A	457361206	457233476	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	11867824	0	0
T1	1363	10	0	0
T2	1816	213	0	0
T3	1550	1	0	0
T4	1191	1	0	0
T5	1690	8	0	0
T6	12330	2114	0	0
T7	2296	322	0	0
T8	1110	47	0	0
T9	796	15	0	0
T10	6795	29	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	457233476	0	0
T1	1363	1275	0	0
T2	1816	1728	0	0
T3	1550	1490	0	0
T4	1191	1124	0	0
T5	1690	1614	0	0
T6	12330	12280	0	0
T7	2296	2197	0	0
T8	1110	1010	0	0
T9	796	701	0	0
T10	6795	6721	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0