Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	457361206	3420	0	0
addr_swap_data_rd_A	457361206	957	0	0
addr_swap_mask_rd_A	457361206	1273	0	0
cfg_rd_A	457361206	1426	0	0
cmd_filter_0_rd_A	457361206	7812	0	0
cmd_filter_1_rd_A	457361206	7284	0	0
cmd_filter_2_rd_A	457361206	7104	0	0
cmd_filter_3_rd_A	457361206	7029	0	0
cmd_filter_4_rd_A	457361206	7339	0	0
cmd_filter_5_rd_A	457361206	7383	0	0
cmd_filter_6_rd_A	457361206	6952	0	0
cmd_filter_7_rd_A	457361206	7420	0	0
cmd_info_0_rd_A	457361206	3208	0	0
cmd_info_10_rd_A	457361206	3323	0	0
cmd_info_11_rd_A	457361206	2844	0	0
cmd_info_12_rd_A	457361206	3862	0	0
cmd_info_13_rd_A	457361206	3068	0	0
cmd_info_14_rd_A	457361206	3376	0	0
cmd_info_15_rd_A	457361206	3177	0	0
cmd_info_16_rd_A	457361206	3354	0	0
cmd_info_17_rd_A	457361206	3718	0	0
cmd_info_18_rd_A	457361206	3154	0	0
cmd_info_19_rd_A	457361206	3287	0	0
cmd_info_1_rd_A	457361206	3803	0	0
cmd_info_20_rd_A	457361206	3731	0	0
cmd_info_21_rd_A	457361206	3081	0	0
cmd_info_22_rd_A	457361206	3516	0	0
cmd_info_23_rd_A	457361206	3848	0	0
cmd_info_2_rd_A	457361206	3316	0	0
cmd_info_3_rd_A	457361206	3469	0	0
cmd_info_4_rd_A	457361206	3652	0	0
cmd_info_5_rd_A	457361206	3348	0	0
cmd_info_6_rd_A	457361206	3681	0	0
cmd_info_7_rd_A	457361206	3611	0	0
cmd_info_8_rd_A	457361206	3531	0	0
cmd_info_9_rd_A	457361206	3307	0	0
cmd_info_en4b_rd_A	457361206	1371	0	0
cmd_info_ex4b_rd_A	457361206	1367	0	0
cmd_info_wrdi_rd_A	457361206	1407	0	0
cmd_info_wren_rd_A	457361206	1528	0	0
intercept_en_rd_A	457361206	1692	0	0
intr_enable_rd_A	457361206	3217	0	0
jedec_cc_rd_A	457361206	1350	0	0
jedec_id_rd_A	457361206	1454	0	0
mailbox_addr_rd_A	457361206	1215	0	0
payload_swap_data_rd_A	457361206	1104	0	0
payload_swap_mask_rd_A	457361206	1298	0	0
read_threshold_rd_A	457361206	1196	0	0
tpm_access_0_rd_A	457361206	1695	0	0
tpm_access_1_rd_A	457361206	1216	0	0
tpm_cfg_rd_A	457361206	1991	0	0
tpm_did_vid_rd_A	457361206	1272	0	0
tpm_int_enable_rd_A	457361206	1057	0	0
tpm_int_status_rd_A	457361206	1184	0	0
tpm_int_vector_rd_A	457361206	1161	0	0
tpm_intf_capability_rd_A	457361206	1129	0	0
tpm_rid_rd_A	457361206	1147	0	0
tpm_sts_rd_A	457361206	1002	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3420	0	0
T124	6563	77	0	0
T125	2609	2	0	0
T126	14785	118	0	0
T127	28193	1	0	0
T128	27461	2	0	0
T129	9915	2	0	0
T130	17283	197	0	0
T133	13578	232	0	0
T138	2463	1	0	0
T139	15440	8	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	957	0	0
T139	15440	11	0	0
T142	9382	2	0	0
T152	11211	1	0	0
T157	9741	1	0	0
T174	5943	7	0	0
T177	18297	38	0	0
T186	18694	21	0	0
T187	14097	14	0	0
T188	16756	20	0	0
T189	9644	11	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1273	0	0
T139	15440	21	0	0
T142	9382	21	0	0
T152	11211	4	0	0
T157	9741	2	0	0
T174	5943	4	0	0
T177	18297	84	0	0
T186	18694	28	0	0
T187	14097	19	0	0
T188	16756	19	0	0
T189	9644	3	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1426	0	0
T124	6563	2	0	0
T139	15440	50	0	0
T142	9382	4	0	0
T152	11211	37	0	0
T157	9741	14	0	0
T174	5943	1	0	0
T177	18297	62	0	0
T186	18694	18	0	0
T187	14097	40	0	0
T188	16756	30	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	7812	0	0
T139	15440	133	0	0
T142	9382	80	0	0
T152	11211	140	0	0
T157	9741	152	0	0
T174	5943	105	0	0
T177	18297	59	0	0
T186	18694	15	0	0
T187	14097	391	0	0
T188	16756	283	0	0
T189	9644	139	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	7284	0	0
T139	15440	251	0	0
T142	9382	137	0	0
T152	11211	146	0	0
T157	9741	129	0	0
T174	5943	17	0	0
T177	18297	30	0	0
T186	18694	34	0	0
T187	14097	260	0	0
T188	16756	253	0	0
T189	9644	22	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	7104	0	0
T139	15440	238	0	0
T142	9382	10	0	0
T152	11211	6	0	0
T157	9741	137	0	0
T174	5943	4	0	0
T177	18297	66	0	0
T186	18694	24	0	0
T187	14097	30	0	0
T188	16756	296	0	0
T189	9644	149	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	7029	0	0
T139	15440	112	0	0
T142	9382	42	0	0
T152	11211	371	0	0
T157	9741	126	0	0
T174	5943	83	0	0
T177	18297	78	0	0
T186	18694	31	0	0
T187	14097	187	0	0
T188	16756	204	0	0
T189	9644	124	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	7339	0	0
T139	15440	272	0	0
T142	9382	75	0	0
T152	11211	150	0	0
T157	9741	63	0	0
T174	5943	98	0	0
T177	18297	42	0	0
T186	18694	9	0	0
T187	14097	156	0	0
T188	16756	360	0	0
T189	9644	14	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	7383	0	0
T139	15440	223	0	0
T142	9382	60	0	0
T152	11211	224	0	0
T157	9741	111	0	0
T174	5943	76	0	0
T177	18297	101	0	0
T186	18694	26	0	0
T187	14097	144	0	0
T188	16756	400	0	0
T189	9644	106	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	6952	0	0
T139	15440	125	0	0
T142	9382	82	0	0
T152	11211	127	0	0
T157	9741	9	0	0
T174	5943	48	0	0
T177	18297	32	0	0
T186	18694	45	0	0
T187	14097	129	0	0
T188	16756	282	0	0
T189	9644	153	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	7420	0	0
T139	15440	135	0	0
T142	9382	69	0	0
T152	11211	132	0	0
T157	9741	48	0	0
T159	72056	398	0	0
T177	18297	98	0	0
T186	18694	33	0	0
T187	14097	279	0	0
T188	16756	368	0	0
T189	9644	125	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3208	0	0
T139	15440	20	0	0
T142	9382	12	0	0
T152	11211	4	0	0
T157	9741	10	0	0
T174	5943	52	0	0
T177	18297	75	0	0
T186	18694	23	0	0
T187	14097	81	0	0
T188	16756	123	0	0
T189	9644	11	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3323	0	0
T139	15440	124	0	0
T142	9382	83	0	0
T152	11211	111	0	0
T157	9741	54	0	0
T174	5943	4	0	0
T177	18297	88	0	0
T186	18694	16	0	0
T187	14097	94	0	0
T188	16756	135	0	0
T189	9644	84	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	2844	0	0
T139	15440	14	0	0
T142	9382	37	0	0
T152	11211	43	0	0
T157	9741	26	0	0
T174	5943	21	0	0
T177	18297	56	0	0
T186	18694	64	0	0
T187	14097	65	0	0
T188	16756	100	0	0
T189	9644	97	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3862	0	0
T139	15440	70	0	0
T142	9382	42	0	0
T152	11211	104	0	0
T157	9741	17	0	0
T174	5943	12	0	0
T177	18297	73	0	0
T186	18694	38	0	0
T187	14097	69	0	0
T188	16756	122	0	0
T189	9644	58	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3068	0	0
T126	14785	1	0	0
T139	15440	109	0	0
T142	9382	26	0	0
T152	11211	117	0	0
T157	9741	39	0	0
T174	5943	21	0	0
T177	18297	43	0	0
T186	18694	49	0	0
T187	14097	58	0	0
T188	16756	114	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3376	0	0
T139	15440	135	0	0
T142	9382	26	0	0
T152	11211	55	0	0
T157	9741	56	0	0
T174	5943	13	0	0
T177	18297	58	0	0
T186	18694	30	0	0
T187	14097	33	0	0
T188	16756	146	0	0
T189	9644	49	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3177	0	0
T139	15440	112	0	0
T142	9382	29	0	0
T152	11211	62	0	0
T157	9741	28	0	0
T174	5943	38	0	0
T177	18297	42	0	0
T186	18694	40	0	0
T187	14097	84	0	0
T188	16756	92	0	0
T189	9644	52	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3354	0	0
T139	15440	54	0	0
T142	9382	17	0	0
T152	11211	101	0	0
T157	9741	28	0	0
T174	5943	5	0	0
T177	18297	88	0	0
T186	18694	60	0	0
T187	14097	123	0	0
T188	16756	120	0	0
T189	9644	51	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3718	0	0
T139	15440	86	0	0
T142	9382	28	0	0
T152	11211	142	0	0
T157	9741	121	0	0
T174	5943	17	0	0
T177	18297	33	0	0
T186	18694	35	0	0
T187	14097	61	0	0
T188	16756	60	0	0
T189	9644	110	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3154	0	0
T139	15440	68	0	0
T142	9382	36	0	0
T152	11211	119	0	0
T157	9741	59	0	0
T174	5943	16	0	0
T177	18297	31	0	0
T186	18694	14	0	0
T187	14097	97	0	0
T188	16756	114	0	0
T189	9644	64	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3287	0	0
T139	15440	147	0	0
T142	9382	9	0	0
T152	11211	5	0	0
T157	9741	49	0	0
T174	5943	2	0	0
T177	18297	43	0	0
T186	18694	21	0	0
T187	14097	108	0	0
T188	16756	29	0	0
T189	9644	63	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3803	0	0
T139	15440	114	0	0
T142	9382	29	0	0
T152	11211	134	0	0
T157	9741	53	0	0
T174	5943	70	0	0
T177	18297	86	0	0
T186	18694	23	0	0
T187	14097	114	0	0
T188	16756	63	0	0
T189	9644	14	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3731	0	0
T139	15440	113	0	0
T142	9382	61	0	0
T152	11211	150	0	0
T157	9741	29	0	0
T174	5943	4	0	0
T177	18297	31	0	0
T186	18694	38	0	0
T187	14097	97	0	0
T188	16756	116	0	0
T189	9644	11	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3081	0	0
T139	15440	16	0	0
T142	9382	19	0	0
T152	11211	62	0	0
T157	9741	34	0	0
T174	5943	8	0	0
T177	18297	20	0	0
T186	18694	8	0	0
T187	14097	86	0	0
T188	16756	100	0	0
T189	9644	50	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3516	0	0
T139	15440	144	0	0
T142	9382	4	0	0
T152	11211	58	0	0
T157	9741	5	0	0
T174	5943	23	0	0
T177	18297	48	0	0
T186	18694	51	0	0
T187	14097	61	0	0
T188	16756	155	0	0
T189	9644	73	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3848	0	0
T139	15440	102	0	0
T142	9382	27	0	0
T152	11211	117	0	0
T157	9741	89	0	0
T174	5943	31	0	0
T177	18297	143	0	0
T186	18694	48	0	0
T187	14097	133	0	0
T188	16756	57	0	0
T189	9644	57	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3316	0	0
T139	15440	47	0	0
T142	9382	13	0	0
T152	11211	84	0	0
T157	9741	42	0	0
T174	5943	46	0	0
T177	18297	23	0	0
T186	18694	29	0	0
T187	14097	28	0	0
T188	16756	26	0	0
T189	9644	51	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3469	0	0
T139	15440	115	0	0
T142	9382	37	0	0
T152	11211	114	0	0
T157	9741	48	0	0
T174	5943	33	0	0
T177	18297	48	0	0
T186	18694	30	0	0
T187	14097	125	0	0
T188	16756	100	0	0
T189	9644	138	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3652	0	0
T139	15440	80	0	0
T142	9382	51	0	0
T152	11211	141	0	0
T157	9741	21	0	0
T159	72056	469	0	0
T177	18297	89	0	0
T186	18694	42	0	0
T187	14097	26	0	0
T188	16756	157	0	0
T189	9644	54	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3348	0	0
T139	15440	55	0	0
T142	9382	70	0	0
T152	11211	12	0	0
T157	9741	17	0	0
T174	5943	5	0	0
T177	18297	94	0	0
T186	18694	22	0	0
T187	14097	72	0	0
T188	16756	100	0	0
T189	9644	17	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3681	0	0
T139	15440	68	0	0
T142	9382	26	0	0
T152	11211	91	0	0
T157	9741	65	0	0
T174	5943	24	0	0
T177	18297	38	0	0
T186	18694	61	0	0
T187	14097	51	0	0
T188	16756	189	0	0
T189	9644	9	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3611	0	0
T139	15440	157	0	0
T142	9382	35	0	0
T152	11211	61	0	0
T157	9741	63	0	0
T174	5943	37	0	0
T177	18297	63	0	0
T186	18694	23	0	0
T187	14097	80	0	0
T188	16756	92	0	0
T189	9644	52	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3531	0	0
T139	15440	87	0	0
T152	11211	48	0	0
T157	9741	12	0	0
T159	72056	457	0	0
T174	5943	46	0	0
T177	18297	48	0	0
T186	18694	64	0	0
T187	14097	78	0	0
T188	16756	115	0	0
T189	9644	62	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3307	0	0
T139	15440	84	0	0
T142	9382	6	0	0
T152	11211	96	0	0
T157	9741	56	0	0
T174	5943	43	0	0
T177	18297	64	0	0
T186	18694	42	0	0
T187	14097	161	0	0
T188	16756	82	0	0
T189	9644	55	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1371	0	0
T139	15440	40	0	0
T142	9382	6	0	0
T152	11211	8	0	0
T157	9741	9	0	0
T174	5943	2	0	0
T177	18297	79	0	0
T186	18694	43	0	0
T187	14097	21	0	0
T188	16756	27	0	0
T189	9644	20	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1367	0	0
T139	15440	15	0	0
T142	9382	20	0	0
T152	11211	30	0	0
T157	9741	13	0	0
T174	5943	3	0	0
T177	18297	77	0	0
T186	18694	39	0	0
T187	14097	34	0	0
T188	16756	22	0	0
T189	9644	15	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1407	0	0
T139	15440	34	0	0
T142	9382	18	0	0
T152	11211	23	0	0
T157	9741	6	0	0
T174	5943	4	0	0
T177	18297	92	0	0
T186	18694	27	0	0
T187	14097	28	0	0
T188	16756	37	0	0
T189	9644	15	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1528	0	0
T139	15440	30	0	0
T142	9382	4	0	0
T152	11211	15	0	0
T157	9741	12	0	0
T174	5943	2	0	0
T177	18297	59	0	0
T186	18694	33	0	0
T187	14097	24	0	0
T188	16756	25	0	0
T189	9644	22	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1692	0	0
T139	15440	61	0	0
T142	9382	9	0	0
T152	11211	15	0	0
T157	9741	28	0	0
T159	72056	452	0	0
T177	18297	49	0	0
T186	18694	25	0	0
T187	14097	31	0	0
T188	16756	35	0	0
T189	9644	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	3217	0	0
T34	184899	41	0	0
T35	5905	0	0	0
T36	0	96	0	0
T38	0	156	0	0
T61	105901	0	0	0
T75	33045	0	0	0
T116	7891	0	0	0
T181	114403	0	0	0
T190	0	48	0	0
T191	0	25	0	0
T192	0	39	0	0
T193	0	19	0	0
T194	0	17	0	0
T195	0	57	0	0
T196	0	22	0	0
T197	1182	0	0	0
T198	862	0	0	0
T199	1985	0	0	0
T200	1042	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1350	0	0
T139	15440	21	0	0
T152	11211	22	0	0
T157	9741	7	0	0
T159	72056	446	0	0
T177	18297	73	0	0
T186	18694	69	0	0
T187	14097	37	0	0
T188	16756	28	0	0
T189	9644	10	0	0
T201	37588	42	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1454	0	0
T139	15440	28	0	0
T142	9382	18	0	0
T152	11211	35	0	0
T157	9741	1	0	0
T174	5943	4	0	0
T177	18297	62	0	0
T186	18694	22	0	0
T187	14097	33	0	0
T188	16756	39	0	0
T189	9644	25	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1215	0	0
T139	15440	23	0	0
T142	9382	23	0	0
T152	11211	10	0	0
T157	9741	9	0	0
T174	5943	5	0	0
T177	18297	104	0	0
T186	18694	38	0	0
T187	14097	18	0	0
T188	16756	20	0	0
T189	9644	13	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1104	0	0
T139	15440	15	0	0
T142	9382	6	0	0
T152	11211	3	0	0
T157	9741	7	0	0
T174	5943	5	0	0
T177	18297	71	0	0
T186	18694	22	0	0
T187	14097	24	0	0
T188	16756	12	0	0
T189	9644	19	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1298	0	0
T139	15440	27	0	0
T142	9382	15	0	0
T152	11211	14	0	0
T157	9741	7	0	0
T174	5943	8	0	0
T177	18297	42	0	0
T186	18694	39	0	0
T187	14097	25	0	0
T188	16756	25	0	0
T189	9644	17	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1196	0	0
T139	15440	26	0	0
T142	9382	5	0	0
T152	11211	9	0	0
T159	72056	425	0	0
T174	5943	3	0	0
T177	18297	99	0	0
T186	18694	18	0	0
T187	14097	24	0	0
T188	16756	24	0	0
T189	9644	15	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1695	0	0
T139	15440	32	0	0
T142	9382	16	0	0
T152	11211	26	0	0
T157	9741	26	0	0
T159	72056	493	0	0
T177	18297	71	0	0
T186	18694	28	0	0
T187	14097	47	0	0
T188	16756	41	0	0
T189	9644	26	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1216	0	0
T139	15440	21	0	0
T142	9382	7	0	0
T152	11211	10	0	0
T159	72056	457	0	0
T174	5943	2	0	0
T177	18297	44	0	0
T186	18694	32	0	0
T187	14097	31	0	0
T188	16756	40	0	0
T189	9644	13	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1991	0	0
T139	15440	30	0	0
T142	9382	31	0	0
T152	11211	51	0	0
T157	9741	12	0	0
T174	5943	16	0	0
T177	18297	22	0	0
T186	18694	27	0	0
T187	14097	62	0	0
T188	16756	46	0	0
T189	9644	11	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1272	0	0
T139	15440	13	0	0
T142	9382	7	0	0
T152	11211	27	0	0
T157	9741	5	0	0
T174	5943	9	0	0
T177	18297	55	0	0
T186	18694	55	0	0
T187	14097	20	0	0
T188	16756	23	0	0
T189	9644	20	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1057	0	0
T139	15440	18	0	0
T142	9382	11	0	0
T152	11211	11	0	0
T157	9741	12	0	0
T159	72056	444	0	0
T177	18297	27	0	0
T186	18694	22	0	0
T187	14097	26	0	0
T188	16756	26	0	0
T189	9644	8	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1184	0	0
T139	15440	16	0	0
T142	9382	13	0	0
T152	11211	12	0	0
T157	9741	9	0	0
T159	72056	488	0	0
T177	18297	14	0	0
T186	18694	42	0	0
T187	14097	24	0	0
T188	16756	13	0	0
T189	9644	14	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1161	0	0
T139	15440	5	0	0
T142	9382	6	0	0
T152	11211	11	0	0
T157	9741	10	0	0
T174	5943	9	0	0
T177	18297	92	0	0
T186	18694	27	0	0
T187	14097	28	0	0
T188	16756	19	0	0
T189	9644	23	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1129	0	0
T139	15440	29	0	0
T142	9382	11	0	0
T152	11211	21	0	0
T157	9741	11	0	0
T174	5943	3	0	0
T177	18297	76	0	0
T186	18694	11	0	0
T187	14097	19	0	0
T188	16756	23	0	0
T189	9644	14	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1147	0	0
T139	15440	33	0	0
T142	9382	8	0	0
T152	11211	18	0	0
T159	72056	416	0	0
T174	5943	5	0	0
T177	18297	80	0	0
T186	18694	39	0	0
T187	14097	33	0	0
T188	16756	23	0	0
T189	9644	5	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457361206	1002	0	0
T139	15440	24	0	0
T142	9382	10	0	0
T152	11211	11	0	0
T157	9741	17	0	0
T174	5943	4	0	0
T177	18297	76	0	0
T186	18694	33	0	0
T187	14097	26	0	0
T188	16756	16	0	0
T189	9644	18	0	0