Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3275640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4115099

1

T1

1

T2

106

T4

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3969151	1			T1	53		T2	101		T3	1
values[0x0]	1711855	1			T2	60		T4	14		T5	17
values[0x1]	1709733	1			T2	40		T4	21		T5	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2329778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5060961

1

T1

21

T2

167

T4

52

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25902	1			T2	1		T6	5		T7	6
valid_sources[0x01]	30000	1			T6	3		T7	2		T9	5
valid_sources[0x02]	28914	1			T6	3		T7	3		T9	8
valid_sources[0x03]	31447	1			T6	6		T7	2		T9	6
valid_sources[0x04]	30286	1			T6	2		T7	3		T9	2
valid_sources[0x05]	28349	1			T1	2		T4	1		T6	2
valid_sources[0x06]	30563	1			T6	1		T7	2		T9	7
valid_sources[0x07]	33619	1			T6	7		T7	4		T9	1
valid_sources[0x08]	28218	1			T2	7		T6	2		T7	2
valid_sources[0x09]	30793	1			T1	1		T6	3		T7	8
valid_sources[0x0a]	53377	1			T1	1		T5	1		T6	4
valid_sources[0x0b]	28319	1			T6	6		T7	5		T9	4
valid_sources[0x0c]	25423	1			T1	1		T6	3		T7	6
valid_sources[0x0d]	26855	1			T4	1		T6	8		T7	2
valid_sources[0x0e]	27380	1			T6	5		T7	7		T9	8
valid_sources[0x0f]	27034	1			T6	1		T7	2		T9	6
valid_sources[0x10]	29969	1			T1	1		T5	2		T6	5
valid_sources[0x11]	26026	1			T6	5		T7	8		T9	3
valid_sources[0x12]	46111	1			T4	2		T6	4		T7	3
valid_sources[0x13]	27138	1			T7	2		T9	6		T11	15
valid_sources[0x14]	27209	1			T1	2		T2	1		T6	4
valid_sources[0x15]	39261	1			T6	4		T7	5		T9	5
valid_sources[0x16]	30216	1			T6	3		T7	11		T9	9
valid_sources[0x17]	30217	1			T1	1		T4	1		T6	3
valid_sources[0x18]	43631	1			T6	7		T7	4		T9	10
valid_sources[0x19]	26810	1			T6	2		T7	8		T9	10
valid_sources[0x1a]	28945	1			T6	4		T7	3		T9	1
valid_sources[0x1b]	25845	1			T2	14		T6	3		T7	4
valid_sources[0x1c]	25420	1			T7	12		T9	4		T11	8
valid_sources[0x1d]	27027	1			T6	4		T7	7		T9	4
valid_sources[0x1e]	26510	1			T7	19		T9	6		T11	5
valid_sources[0x1f]	31053	1			T5	5		T6	2		T7	5
valid_sources[0x20]	54397	1			T1	2		T6	2		T7	3
valid_sources[0x21]	26488	1			T6	3		T7	3		T9	4
valid_sources[0x22]	27780	1			T2	6		T6	5		T7	2
valid_sources[0x23]	26685	1			T4	1		T6	2		T7	4
valid_sources[0x24]	25237	1			T6	2		T7	6		T9	2
valid_sources[0x25]	28957	1			T6	4		T7	7		T9	2
valid_sources[0x26]	29777	1			T6	5		T7	11		T9	2
valid_sources[0x27]	26958	1			T6	2		T7	11		T9	10
valid_sources[0x28]	27029	1			T4	1		T7	4		T9	9
valid_sources[0x29]	28599	1			T4	1		T6	4		T9	2
valid_sources[0x2a]	25364	1			T6	3		T7	12		T9	2
valid_sources[0x2b]	27490	1			T6	2		T7	4		T9	10
valid_sources[0x2c]	28016	1			T7	2		T9	3		T11	7
valid_sources[0x2d]	26827	1			T4	1		T6	4		T7	2
valid_sources[0x2e]	31279	1			T4	2		T6	4		T7	4
valid_sources[0x2f]	28258	1			T2	8		T6	4		T7	15
valid_sources[0x30]	28657	1			T6	7		T7	6		T9	7
valid_sources[0x31]	26669	1			T4	1		T6	10		T7	3
valid_sources[0x32]	28000	1			T4	1		T6	3		T7	4
valid_sources[0x33]	29666	1			T4	1		T6	2		T7	4
valid_sources[0x34]	34256	1			T6	1		T7	6		T9	6
valid_sources[0x35]	28509	1			T4	3		T6	4		T7	1
valid_sources[0x36]	30843	1			T1	1		T6	2		T7	6
valid_sources[0x37]	27530	1			T6	6		T7	7		T9	5
valid_sources[0x38]	29135	1			T2	2		T6	4		T7	3
valid_sources[0x39]	29528	1			T2	1		T6	6		T7	6
valid_sources[0x3a]	28570	1			T4	1		T6	3		T7	5
valid_sources[0x3b]	26075	1			T1	1		T2	1		T6	5
valid_sources[0x3c]	31902	1			T4	2		T6	2		T7	1
valid_sources[0x3d]	27569	1			T2	1		T4	1		T6	2
valid_sources[0x3e]	31652	1			T6	1		T7	2		T9	6
valid_sources[0x3f]	28845	1			T5	5		T6	4		T7	3
valid_sources[0x40]	28608	1			T1	1		T6	4		T7	3
valid_sources[0x41]	32082	1			T2	5		T6	7		T7	5
valid_sources[0x42]	26230	1			T7	3		T9	1		T11	12
valid_sources[0x43]	30226	1			T6	5		T7	2		T9	8
valid_sources[0x44]	26435	1			T1	1		T6	3		T7	3
valid_sources[0x45]	27463	1			T1	2		T6	6		T9	6
valid_sources[0x46]	28079	1			T6	4		T7	8		T9	2
valid_sources[0x47]	28430	1			T1	1		T6	5		T7	4
valid_sources[0x48]	34749	1			T1	1		T2	4		T6	6
valid_sources[0x49]	30544	1			T6	2		T7	5		T9	4
valid_sources[0x4a]	26906	1			T6	4		T9	6		T11	2
valid_sources[0x4b]	27699	1			T6	2		T7	4		T9	8
valid_sources[0x4c]	24790	1			T6	4		T7	4		T9	3
valid_sources[0x4d]	25516	1			T2	1		T6	5		T7	3
valid_sources[0x4e]	27110	1			T2	1		T6	5		T7	7
valid_sources[0x4f]	26134	1			T6	4		T7	6		T9	5
valid_sources[0x50]	29264	1			T6	5		T7	12		T9	4
valid_sources[0x51]	25641	1			T6	2		T7	6		T9	1
valid_sources[0x52]	25810	1			T6	1		T7	8		T9	7
valid_sources[0x53]	35082	1			T2	1		T6	2		T7	1
valid_sources[0x54]	27359	1			T6	3		T7	4		T9	3
valid_sources[0x55]	27912	1			T4	2		T6	3		T7	2
valid_sources[0x56]	27316	1			T1	1		T6	8		T7	1
valid_sources[0x57]	34874	1			T6	2		T7	4		T9	6
valid_sources[0x58]	27888	1			T2	6		T6	4		T7	4
valid_sources[0x59]	25496	1			T2	2		T6	5		T7	2
valid_sources[0x5a]	28390	1			T1	1		T4	2		T6	6
valid_sources[0x5b]	28080	1			T4	1		T6	4		T7	8
valid_sources[0x5c]	28150	1			T6	6		T9	6		T11	8
valid_sources[0x5d]	27269	1			T6	9		T7	7		T9	5
valid_sources[0x5e]	29159	1			T4	4		T6	2		T7	11
valid_sources[0x5f]	27718	1			T6	1		T7	1		T9	4
valid_sources[0x60]	25896	1			T6	6		T9	8		T11	7
valid_sources[0x61]	29399	1			T6	3		T7	9		T9	4
valid_sources[0x62]	28818	1			T1	1		T6	3		T7	1
valid_sources[0x63]	32884	1			T6	5		T9	11		T11	14
valid_sources[0x64]	25049	1			T6	3		T7	12		T9	8
valid_sources[0x65]	28840	1			T1	1		T6	8		T7	6
valid_sources[0x66]	28157	1			T6	5		T7	3		T9	11
valid_sources[0x67]	30681	1			T6	4		T7	8		T9	1
valid_sources[0x68]	27631	1			T2	5		T6	3		T7	4
valid_sources[0x69]	28853	1			T6	1		T7	4		T9	6
valid_sources[0x6a]	27864	1			T2	1		T6	4		T7	2
valid_sources[0x6b]	31118	1			T6	3		T7	3		T9	2
valid_sources[0x6c]	27577	1			T4	2		T6	2		T7	8
valid_sources[0x6d]	26298	1			T5	2		T6	1		T7	4
valid_sources[0x6e]	27941	1			T4	1		T6	1		T7	6
valid_sources[0x6f]	27091	1			T6	1		T7	3		T9	1
valid_sources[0x70]	30922	1			T6	4		T9	9		T11	7
valid_sources[0x71]	27189	1			T1	1		T6	4		T7	16
valid_sources[0x72]	27219	1			T2	1		T6	7		T9	6
valid_sources[0x73]	27348	1			T4	1		T6	4		T7	5
valid_sources[0x74]	27180	1			T4	1		T6	3		T7	7
valid_sources[0x75]	26976	1			T5	5		T6	1		T7	5
valid_sources[0x76]	28499	1			T4	1		T6	2		T7	2
valid_sources[0x77]	27176	1			T1	1		T2	3		T4	2
valid_sources[0x78]	25830	1			T1	1		T6	2		T7	5
valid_sources[0x79]	26543	1			T7	1		T9	3		T11	10
valid_sources[0x7a]	26530	1			T6	6		T7	6		T11	4
valid_sources[0x7b]	27927	1			T2	3		T6	1		T7	3
valid_sources[0x7c]	25441	1			T1	1		T6	3		T7	2
valid_sources[0x7d]	29900	1			T2	7		T6	8		T7	9
valid_sources[0x7e]	27844	1			T1	1		T6	2		T7	2
valid_sources[0x7f]	25698	1			T6	2		T7	4		T9	6
valid_sources[0x80]	28460	1			T6	2		T7	1		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

998890

1

T1

1

T2

6

T4

20

values[0x0]

all_enables

biggest_size

1570532

1

T2

60

T4

12

T5

14

values[0x1]

all_enables

biggest_size

1545677

1

T2

40

T4

10

T5

10