Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3295386

1

T1

52

T3

1

T4

35

full_word

4114255

1

T1

1

T4

42

T5

25

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7409221	1			T1	53		T3	1		T4	77
auto[TlIntgErrCmd]	129	1			T105	4		T108	7		T109	10
auto[TlIntgErrData]	143	1			T105	5		T108	8		T109	10
auto[TlIntgErrBoth]	148	1			T105	1		T108	5		T109	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3972773

1

T1

53

T3

1

T4

42

auto[1]

3436868

1

T4

35

T5

31

T6

880

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2973468	1			T1	52		T3	1		T4	22
auto[TlIntgErrNone]	partial	auto[1]	321536	1			T4	13		T5	7		T6	1
auto[TlIntgErrNone]	full_word	auto[0]	999099	1			T1	1		T4	20		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	3115118	1			T4	22		T5	24		T6	879
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T105	2		T108	4		T109	4
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T105	2		T108	3		T109	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T195	1		T196	1		T197	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T109	1		T193	1		T198	1
auto[TlIntgErrData]	partial	auto[0]	77	1			T105	3		T108	2		T109	3
auto[TlIntgErrData]	partial	auto[1]	55	1			T105	2		T108	6		T109	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T109	2		T172	1		T199	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T109	1		T196	1		T200	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T108	4		T109	3		T193	2
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T109	5		T193	6		T201	3
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T109	1		T172	1		T196	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T105	1		T108	1		T109	1