Module Definition
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Module Instance : tb.dut.u_intr_upload_edge

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_readcmd.u_addr_latch_pulse

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.19 96.32 100.00 80.00 84.62 100.00 u_readcmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_csb_sync_rst

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.79 99.29 91.20 91.67 96.77 100.00 u_spi_tpm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_sync.u_sync 100.00 100.00 100.00

Line Coverage for Module : prim_edge_detector ( parameter Width=2,ResetValue=0,EnSync=0 + Width=1,ResetValue=0,EnSync=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_intr_upload_edge

SCORELINE
100.00 100.00
tb.dut.u_readcmd.u_addr_latch_pulse

Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00

41 else begin : g_nosync 42 1/1 assign q_sync_d = d_i; Tests: T1 T2 T3  43 end : g_nosync 44 45 1/1 assign q_sync_o = q_sync_d; Tests: T1 T2 T3  46 47 always_ff @(posedge clk_i or negedge rst_ni) begin 48 2/2 if (!rst_ni) q_sync_q <= ResetValue; Tests: T1 T2 T3  | T1 T2 T3  49 1/1 else q_sync_q <= q_sync_d; Tests: T1 T2 T3  50 end 51 52 1/1 assign q_posedge_pulse_o = q_sync_d & ~q_sync_q; Tests: T1 T2 T3  53 1/1 assign q_negedge_pulse_o = ~q_sync_d & q_sync_q; Tests: T1 T2 T3 

Line Coverage for Module : prim_edge_detector ( parameter Width=1,ResetValue=0,EnSync=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_spi_tpm.u_csb_sync_rst

Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00

44 45 1/1 assign q_sync_o = q_sync_d; Tests: T1 T2 T3  46 47 always_ff @(posedge clk_i or negedge rst_ni) begin 48 2/2 if (!rst_ni) q_sync_q <= ResetValue; Tests: T1 T2 T3  | T1 T2 T3  49 1/1 else q_sync_q <= q_sync_d; Tests: T1 T2 T3  50 end 51 52 1/1 assign q_posedge_pulse_o = q_sync_d & ~q_sync_q; Tests: T1 T2 T3  53 1/1 assign q_negedge_pulse_o = ~q_sync_d & q_sync_q; Tests: T1 T2 T3 

Cond Coverage for Module : prim_edge_detector
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T2,T3

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T4,T5

Branch Coverage for Module : prim_edge_detector
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00


48 if (!rst_ni) q_sync_q <= ResetValue; -1- ==> 49 else q_sync_q <= q_sync_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_intr_upload_edge
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00

41 else begin : g_nosync 42 1/1 assign q_sync_d = d_i; Tests: T1 T2 T3  43 end : g_nosync 44 45 1/1 assign q_sync_o = q_sync_d; Tests: T1 T2 T3  46 47 always_ff @(posedge clk_i or negedge rst_ni) begin 48 2/2 if (!rst_ni) q_sync_q <= ResetValue; Tests: T1 T2 T3  | T1 T2 T3  49 1/1 else q_sync_q <= q_sync_d; Tests: T1 T2 T3  50 end 51 52 1/1 assign q_posedge_pulse_o = q_sync_d & ~q_sync_q; Tests: T1 T2 T3  53 1/1 assign q_negedge_pulse_o = ~q_sync_d & q_sync_q; Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_intr_upload_edge
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00


48 if (!rst_ni) q_sync_q <= ResetValue; -1- ==> 49 else q_sync_q <= q_sync_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00

41 else begin : g_nosync 42 1/1 assign q_sync_d = d_i; Tests: T1 T2 T3  43 end : g_nosync 44 45 1/1 assign q_sync_o = q_sync_d; Tests: T1 T2 T3  46 47 always_ff @(posedge clk_i or negedge rst_ni) begin 48 2/2 if (!rst_ni) q_sync_q <= ResetValue; Tests: T1 T2 T3  | T1 T2 T3  49 1/1 else q_sync_q <= q_sync_d; Tests: T6 T7 T9  50 end 51 52 1/1 assign q_posedge_pulse_o = q_sync_d & ~q_sync_q; Tests: T1 T2 T3  53 1/1 assign q_negedge_pulse_o = ~q_sync_d & q_sync_q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT7,T9,T11
10CoveredT6,T7,T9
11CoveredT1,T2,T3

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT6,T7,T9
10CoveredT7,T9,T11
11CoveredT7,T9,T11

Branch Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00


48 if (!rst_ni) q_sync_q <= ResetValue; -1- ==> 49 else q_sync_q <= q_sync_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T6,T7,T9

Line Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00

44 45 1/1 assign q_sync_o = q_sync_d; Tests: T1 T2 T3  46 47 always_ff @(posedge clk_i or negedge rst_ni) begin 48 2/2 if (!rst_ni) q_sync_q <= ResetValue; Tests: T1 T2 T3  | T1 T2 T3  49 1/1 else q_sync_q <= q_sync_d; Tests: T1 T2 T3  50 end 51 52 1/1 assign q_posedge_pulse_o = q_sync_d & ~q_sync_q; Tests: T1 T2 T3  53 1/1 assign q_negedge_pulse_o = ~q_sync_d & q_sync_q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00


48 if (!rst_ni) q_sync_q <= ResetValue; -1- ==> 49 else q_sync_q <= q_sync_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%