Line Coverage for Module :
prim_fifo_async_sram_adapter ( parameter Width=16,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=960,DepthW=5,PtrVW=4,PtrW=5 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 86 | 86 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
| ALWAYS | 168 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| ALWAYS | 204 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 248 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
| ALWAYS | 270 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
| ALWAYS | 324 | 9 | 9 | 100.00 |
| ROUTINE | 347 | 7 | 7 | 100.00 |
| ROUTINE | 368 | 9 | 9 | 100.00 |
120 // Begin: Write pointer sync to read clock ========================
121 1/1 assign w_wptr_inc = wvalid_i & wready_o;
Tests: T1 T2 T3
122
123 1/1 assign w_wptr_d = w_wptr_q + PtrW'(1);
Tests: T1 T2 T3
124
125 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
126 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
127 1/1 w_wptr_q <= PtrW'(0);
Tests: T1 T2 T3
128 1/1 w_wptr_gray_q <= PtrW'(0);
Tests: T1 T2 T3
129 1/1 end else if (w_wptr_inc) begin
Tests: T4 T5 T6
130 1/1 w_wptr_q <= w_wptr_d;
Tests: T44 T42 T32
131 1/1 w_wptr_gray_q <= w_wptr_gray_d;
Tests: T44 T42 T32
132 end
MISSING_ELSE
133 end
134
135 1/1 assign w_wptr_v = w_wptr_q[0+:PtrVW];
Tests: T1 T2 T3
136 1/1 assign w_wptr_p = w_wptr_q[PtrW-1];
Tests: T1 T2 T3
137
138 1/1 assign w_wptr_gray_d = dec2gray(w_wptr_d);
Tests: T1 T2 T3
139
140 prim_flop_2sync #(
141 .Width (PtrW)
142 ) u_sync_wptr_gray (
143 .clk_i (clk_rd_i),
144 .rst_ni (rst_rd_ni),
145 .d_i (w_wptr_gray_q),
146 .q_o (r_wptr_gray)
147 );
148
149 1/1 assign r_wptr = gray2dec(r_wptr_gray);
Tests: T1 T2 T3
150 1/1 assign r_wptr_p = r_wptr[PtrW-1];
Tests: T1 T2 T3
151 1/1 assign r_wptr_v = r_wptr[0+:PtrVW];
Tests: T1 T2 T3
152
153 1/1 assign wdepth_o = (w_wptr_p == w_rptr_p)
Tests: T1 T2 T3
154 ? DepthW'(w_wptr_v - w_rptr_v)
155 : DepthW'({1'b1, w_wptr_v} - {1'b 0, w_rptr_v});
156 // End: Write pointer sync to read clock ------------------------
157
158 // Begin: Read pointer sync to write clock ========================
159 //assign r_rptr_inc = rvalid_o & rready_i;
160 //assign r_rptr_inc = r_sram_req_o && r_sram_gnt_i;
161 // Increase the read pointer (crossing the clock domain) only when the
162 // reader acked.
163 1/1 assign r_rptr_inc = rfifo_ack;
Tests: T44 T42 T32
164
165 1/1 assign r_rptr_d = r_rptr_q + PtrW'(1);
Tests: T1 T2 T3
166
167 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
168 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
169 1/1 r_rptr_q <= PtrW'(0);
Tests: T1 T2 T3
170 1/1 r_rptr_gray_q <= PtrW'(0);
Tests: T1 T2 T3
171 1/1 end else if (r_rptr_inc) begin
Tests: T1 T2 T3
172 1/1 r_rptr_q <= r_rptr_d;
Tests: T44 T42 T32
173 1/1 r_rptr_gray_q <= r_rptr_gray_d;
Tests: T44 T42 T32
174 end
MISSING_ELSE
175 end
176
177 1/1 assign r_rptr_v = r_rptr_q[0+:PtrVW];
Tests: T1 T2 T3
178 1/1 assign r_rptr_p = r_rptr_q[PtrW-1];
Tests: T1 T2 T3
179
180 1/1 assign r_rptr_gray_d = dec2gray(r_rptr_d);
Tests: T1 T2 T3
181
182 prim_flop_2sync #(
183 .Width (PtrW)
184 ) u_sync_rptr_gray (
185 .clk_i (clk_wr_i),
186 .rst_ni (rst_wr_ni),
187 .d_i (r_rptr_gray_q),
188 .q_o (w_rptr_gray)
189 );
190
191 1/1 assign w_rptr = gray2dec(w_rptr_gray);
Tests: T1 T2 T3
192 1/1 assign w_rptr_p = w_rptr[PtrW-1];
Tests: T1 T2 T3
193 1/1 assign w_rptr_v = w_rptr[0+:PtrVW];
Tests: T1 T2 T3
194
195 1/1 assign rdepth_o = (r_wptr_p == r_rptr_p)
Tests: T1 T2 T3
196 ? DepthW'(r_wptr_v - r_rptr_v)
197 : DepthW'({1'b1, r_wptr_v} - {1'b 0, r_rptr_v});
198 // End: Read pointer sync to write clock ------------------------
199
200 // Begin: SRAM Read pointer
201 1/1 assign r_sram_rptr_inc = rsram_ack;
Tests: T1 T2 T3
202
203 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
204 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
205 1/1 r_sram_rptr <= PtrW'(0);
Tests: T1 T2 T3
206 1/1 end else if (r_sram_rptr_inc) begin
Tests: T1 T2 T3
207 1/1 r_sram_rptr <= r_sram_rptr + PtrW'(1);
Tests: T44 T42 T32
208 end
MISSING_ELSE
209 end
210
211 1/1 assign r_sramrptr_empty = (r_wptr == r_sram_rptr);
Tests: T1 T2 T3
212 // End: SRAM Read pointer
213
214 // Full/ Empty
215 // Lint complains PtrW'(1) << (PtrW-1). So changed as below
216 localparam logic [PtrW-1:0] XorMask = {1'b 1, {PtrW-1{1'b0}}};
217 1/1 assign w_full = (w_wptr_q == (w_rptr ^ XorMask));
Tests: T1 T2 T3
218 1/1 assign r_full = (r_wptr == (r_rptr_q ^ XorMask));
Tests: T1 T2 T3
219 1/1 assign r_empty = (r_wptr == r_rptr_q);
Tests: T1 T2 T3
220
221 logic unused_r_empty;
222 1/1 assign unused_r_empty = r_empty;
Tests: T1 T2 T3
223
224 1/1 assign r_full_o = r_full;
Tests: T1 T2 T3
225 1/1 assign w_full_o = w_full;
Tests: T1 T2 T3
226
227 // The notempty status !(wptr == rptr) assert one clock earlier than the
228 // actual `rvalid` signals.
229 //
230 // The reason is due to the SRAM read latency. The module uses SRAM FIFO
231 // interface. When the logic in producer domain pushes entries, the pointer
232 // is increased. This triggers the FIFO logic in the consumer clock domain
233 // fetches data from SRAM.
234 //
235 // The pointer crosses the clock boundary. It takes usually two cycles (in
236 // the consumer side). Then, as the read and write pointer in the read clock
237 // domain has a gap by 1, the FIFO not empty status is raised.
238 //
239 // At this time, the logic just sent the read request to the SRAM. The data
240 // is not yet read. The `rvalid` asserts when it receives data from the
241 // SRAM.
242 //
243 // So, if the consumer reads data at the same cycle when notempty status is
244 // raised, it reads incorrect data.
245 1/1 assign r_notempty_o = rvalid_o;
Tests: T1 T2 T3
246
247 1/1 assign rsram_ack = r_sram_req_o && r_sram_gnt_i;
Tests: T1 T2 T3
248 1/1 assign rfifo_ack = rvalid_o && rready_i;
Tests: T1 T2 T3
249
250 // SRAM Write Request
251 1/1 assign w_sram_req_o = wvalid_i && !w_full;
Tests: T1 T2 T3
252 1/1 assign wready_o = !w_full && w_sram_gnt_i;
Tests: T1 T2 T3
253 assign w_sram_write_o = 1'b 1; // Always write
254 1/1 assign w_sram_addr_o = SramBaseAddr + SramAw'(w_wptr_v);
Tests: T1 T2 T3
255
256 1/1 assign w_sram_wdata_o = SramDw'(wdata_i);
Tests: T1 T2 T3
257 assign w_sram_wmask_o = SramDw'({Width{1'b1}});
258
259 logic unused_w_sram;
260 1/1 assign unused_w_sram = ^{w_sram_rvalid_i, w_sram_rdata_i, w_sram_rerror_i};
Tests: T1 T2 T3
261
262 // SRAM Read Request
263 // Request Scenario (!r_empty):
264 // - storage empty: Send request if
265 // !r_sram_rvalid_i || (rfifo_ack && r_sram_rvalid_i);
266 // - storage !empty: depends on the rfifo_ack:
267 // - r_rptr_inc: Can request more
268 // - !r_rptr_inc: Can't request
269 always_comb begin : r_sram_req
270 1/1 r_sram_req_o = 1'b 0;
Tests: T1 T2 T3
271 // Karnough Map (!empty): sram_req
272 // {sram_rv, rfifo_ack} | 00 | 01 | 11 | 10
273 // ----------------------------------------------------------
274 // stored | 0 | 1 | impossible | 1 | 0
275 // | 1 | 0 | 1 | X | impossible
276 //
277 // req_o = r_ptr_inc || (!stored && !r_sram_rvalid_i)
278
279 1/1 if (stored) begin
Tests: T1 T2 T3
280 // storage has data. depends on rfifo_ack
281 // rfifo_ack can be replaced to rready_i as `rvalid_o` is 1
282 1/1 r_sram_req_o = !r_sramrptr_empty && rfifo_ack;
Tests: T44 T42 T32
283 end else begin
284 // storage has no data.
285 // Can send request only when the reader accept the request or no
286 // previous request sent out.
287 1/1 r_sram_req_o = !r_sramrptr_empty && !(r_sram_rvalid_i ^ rfifo_ack);
Tests: T1 T2 T3
288 end
289 end : r_sram_req
290
291 1/1 assign rvalid_o = stored || r_sram_rvalid_i;
Tests: T1 T2 T3
292 assign r_sram_write_o = 1'b 0; // always read
293 assign r_sram_wdata_o = '0;
294 assign r_sram_wmask_o = '0;
295
296 // Send SRAM request with sram read pointer.
297 1/1 assign r_sram_addr_o = SramBaseAddr + SramAw'(r_sram_rptr[0+:PtrVW]);
Tests: T1 T2 T3
298
299 1/1 assign rdata_d = (r_sram_rvalid_i) ? r_sram_rdata_i[0+:Width] : Width'(0);
Tests: T1 T2 T3
300
301 1/1 assign rdata_o = (stored) ? rdata_q : rdata_d;
Tests: T1 T2 T3
302
303 logic unused_rsram;
304 1/1 assign unused_rsram = ^{r_sram_rerror_i};
Tests: T1 T2 T3
305
306 if (Width < SramDw) begin : g_unused_rdata
307 logic unused_rdata;
308 1/1 assign unused_rdata = ^r_sram_rdata_i[SramDw-1:Width];
Tests: T2 T4 T25
309 end : g_unused_rdata
310
311 // read clock domain rdata storage
312 logic store_en;
313
314 // Karnough Map (r_sram_rvalid_i):
315 // rfifo_ack | 0 | 1 |
316 // ---------------------
317 // stored 0 | 1 | 0 |
318 // 1 | 0 | 1 |
319 //
320 // stored = s.r.v && XNOR(stored, rptr_inc)
321 1/1 assign store_en = r_sram_rvalid_i && !(stored ^ rfifo_ack);
Tests: T1 T2 T3
322
323 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
324 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
325 1/1 stored <= 1'b 0;
Tests: T1 T2 T3
326 1/1 rdata_q <= Width'(0);
Tests: T1 T2 T3
327 1/1 end else if (store_en) begin
Tests: T1 T2 T3
328 1/1 stored <= 1'b 1;
Tests: T44 T42 T32
329 1/1 rdata_q <= rdata_d;
Tests: T44 T42 T32
330 1/1 end else if (!r_sram_rvalid_i && rfifo_ack) begin
Tests: T1 T2 T3
331 // No request sent, host reads the data
332 1/1 stored <= 1'b 0;
Tests: T44 T42 T32
333 1/1 rdata_q <= Width'(0);
Tests: T44 T42 T32
334 end
MISSING_ELSE
335 end
336
337 //////////////
338 // Function //
339 //////////////
340
341 // dec2gray / gray2dec copied from prim_fifo_async.sv
342 function automatic [PtrW-1:0] dec2gray(input logic [PtrW-1:0] decval);
343 logic [PtrW-1:0] decval_sub;
344 logic [PtrW-1:0] decval_in;
345 logic unused_decval_msb;
346
347 1/1 decval_sub = (PtrW)'(Depth) - {1'b0, decval[PtrW-2:0]} - 1'b1;
Tests: T1 T2 T3
348
349 1/1 decval_in = decval[PtrW-1] ? decval_sub : decval;
Tests: T1 T2 T3
350
351 // We do not care about the MSB, hence we mask it out
352 1/1 unused_decval_msb = decval_in[PtrW-1];
Tests: T1 T2 T3
353 1/1 decval_in[PtrW-1] = 1'b0;
Tests: T1 T2 T3
354
355 // Perform the XOR conversion
356 1/1 dec2gray = decval_in;
Tests: T1 T2 T3
357 1/1 dec2gray ^= (decval_in >> 1);
Tests: T1 T2 T3
358
359 // Override the MSB
360 1/1 dec2gray[PtrW-1] = decval[PtrW-1];
Tests: T1 T2 T3
361 endfunction
362
363 // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
364 function automatic [PtrW-1:0] gray2dec(input logic [PtrW-1:0] grayval);
365 logic [PtrW-1:0] dec_tmp, dec_tmp_sub;
366 logic unused_decsub_msb;
367
368 1/1 dec_tmp = '0;
Tests: T1 T2 T3
369 1/1 for (int i = PtrW-2; i >= 0; i--) begin
Tests: T1 T2 T3
370 1/1 dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
Tests: T1 T2 T3
371 end
372 1/1 dec_tmp_sub = (PtrW)'(Depth) - dec_tmp - 1'b1;
Tests: T1 T2 T3
373 1/1 if (grayval[PtrW-1]) begin
Tests: T1 T2 T3
374 1/1 gray2dec = dec_tmp_sub;
Tests: T50 T85 T65
375 // Override MSB
376 1/1 gray2dec[PtrW-1] = 1'b1;
Tests: T50 T85 T65
377 1/1 unused_decsub_msb = dec_tmp_sub[PtrW-1];
Tests: T50 T85 T65
378 end else begin
379 1/1 gray2dec = dec_tmp;
Tests: T1 T2 T3
Line Coverage for Module :
prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=976,DepthW=5,PtrVW=4,PtrW=5 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 85 | 85 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
| ALWAYS | 168 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| ALWAYS | 204 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 248 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
| ALWAYS | 270 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
| ALWAYS | 324 | 9 | 9 | 100.00 |
| ROUTINE | 347 | 7 | 7 | 100.00 |
| ROUTINE | 368 | 9 | 9 | 100.00 |
120 // Begin: Write pointer sync to read clock ========================
121 1/1 assign w_wptr_inc = wvalid_i & wready_o;
Tests: T1 T2 T3
122
123 1/1 assign w_wptr_d = w_wptr_q + PtrW'(1);
Tests: T1 T2 T3
124
125 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
126 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
127 1/1 w_wptr_q <= PtrW'(0);
Tests: T1 T2 T3
128 1/1 w_wptr_gray_q <= PtrW'(0);
Tests: T1 T2 T3
129 1/1 end else if (w_wptr_inc) begin
Tests: T4 T5 T6
130 1/1 w_wptr_q <= w_wptr_d;
Tests: T44 T42 T32
131 1/1 w_wptr_gray_q <= w_wptr_gray_d;
Tests: T44 T42 T32
132 end
MISSING_ELSE
133 end
134
135 1/1 assign w_wptr_v = w_wptr_q[0+:PtrVW];
Tests: T1 T2 T3
136 1/1 assign w_wptr_p = w_wptr_q[PtrW-1];
Tests: T1 T2 T3
137
138 1/1 assign w_wptr_gray_d = dec2gray(w_wptr_d);
Tests: T1 T2 T3
139
140 prim_flop_2sync #(
141 .Width (PtrW)
142 ) u_sync_wptr_gray (
143 .clk_i (clk_rd_i),
144 .rst_ni (rst_rd_ni),
145 .d_i (w_wptr_gray_q),
146 .q_o (r_wptr_gray)
147 );
148
149 1/1 assign r_wptr = gray2dec(r_wptr_gray);
Tests: T1 T2 T3
150 1/1 assign r_wptr_p = r_wptr[PtrW-1];
Tests: T1 T2 T3
151 1/1 assign r_wptr_v = r_wptr[0+:PtrVW];
Tests: T1 T2 T3
152
153 1/1 assign wdepth_o = (w_wptr_p == w_rptr_p)
Tests: T1 T2 T3
154 ? DepthW'(w_wptr_v - w_rptr_v)
155 : DepthW'({1'b1, w_wptr_v} - {1'b 0, w_rptr_v});
156 // End: Write pointer sync to read clock ------------------------
157
158 // Begin: Read pointer sync to write clock ========================
159 //assign r_rptr_inc = rvalid_o & rready_i;
160 //assign r_rptr_inc = r_sram_req_o && r_sram_gnt_i;
161 // Increase the read pointer (crossing the clock domain) only when the
162 // reader acked.
163 1/1 assign r_rptr_inc = rfifo_ack;
Tests: T44 T42 T32
164
165 1/1 assign r_rptr_d = r_rptr_q + PtrW'(1);
Tests: T1 T2 T3
166
167 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
168 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
169 1/1 r_rptr_q <= PtrW'(0);
Tests: T1 T2 T3
170 1/1 r_rptr_gray_q <= PtrW'(0);
Tests: T1 T2 T3
171 1/1 end else if (r_rptr_inc) begin
Tests: T1 T2 T3
172 1/1 r_rptr_q <= r_rptr_d;
Tests: T44 T42 T32
173 1/1 r_rptr_gray_q <= r_rptr_gray_d;
Tests: T44 T42 T32
174 end
MISSING_ELSE
175 end
176
177 1/1 assign r_rptr_v = r_rptr_q[0+:PtrVW];
Tests: T1 T2 T3
178 1/1 assign r_rptr_p = r_rptr_q[PtrW-1];
Tests: T1 T2 T3
179
180 1/1 assign r_rptr_gray_d = dec2gray(r_rptr_d);
Tests: T1 T2 T3
181
182 prim_flop_2sync #(
183 .Width (PtrW)
184 ) u_sync_rptr_gray (
185 .clk_i (clk_wr_i),
186 .rst_ni (rst_wr_ni),
187 .d_i (r_rptr_gray_q),
188 .q_o (w_rptr_gray)
189 );
190
191 1/1 assign w_rptr = gray2dec(w_rptr_gray);
Tests: T1 T2 T3
192 1/1 assign w_rptr_p = w_rptr[PtrW-1];
Tests: T1 T2 T3
193 1/1 assign w_rptr_v = w_rptr[0+:PtrVW];
Tests: T1 T2 T3
194
195 1/1 assign rdepth_o = (r_wptr_p == r_rptr_p)
Tests: T1 T2 T3
196 ? DepthW'(r_wptr_v - r_rptr_v)
197 : DepthW'({1'b1, r_wptr_v} - {1'b 0, r_rptr_v});
198 // End: Read pointer sync to write clock ------------------------
199
200 // Begin: SRAM Read pointer
201 1/1 assign r_sram_rptr_inc = rsram_ack;
Tests: T1 T2 T3
202
203 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
204 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
205 1/1 r_sram_rptr <= PtrW'(0);
Tests: T1 T2 T3
206 1/1 end else if (r_sram_rptr_inc) begin
Tests: T1 T2 T3
207 1/1 r_sram_rptr <= r_sram_rptr + PtrW'(1);
Tests: T44 T42 T32
208 end
MISSING_ELSE
209 end
210
211 1/1 assign r_sramrptr_empty = (r_wptr == r_sram_rptr);
Tests: T1 T2 T3
212 // End: SRAM Read pointer
213
214 // Full/ Empty
215 // Lint complains PtrW'(1) << (PtrW-1). So changed as below
216 localparam logic [PtrW-1:0] XorMask = {1'b 1, {PtrW-1{1'b0}}};
217 1/1 assign w_full = (w_wptr_q == (w_rptr ^ XorMask));
Tests: T1 T2 T3
218 1/1 assign r_full = (r_wptr == (r_rptr_q ^ XorMask));
Tests: T1 T2 T3
219 1/1 assign r_empty = (r_wptr == r_rptr_q);
Tests: T1 T2 T3
220
221 logic unused_r_empty;
222 1/1 assign unused_r_empty = r_empty;
Tests: T1 T2 T3
223
224 1/1 assign r_full_o = r_full;
Tests: T1 T2 T3
225 1/1 assign w_full_o = w_full;
Tests: T1 T2 T3
226
227 // The notempty status !(wptr == rptr) assert one clock earlier than the
228 // actual `rvalid` signals.
229 //
230 // The reason is due to the SRAM read latency. The module uses SRAM FIFO
231 // interface. When the logic in producer domain pushes entries, the pointer
232 // is increased. This triggers the FIFO logic in the consumer clock domain
233 // fetches data from SRAM.
234 //
235 // The pointer crosses the clock boundary. It takes usually two cycles (in
236 // the consumer side). Then, as the read and write pointer in the read clock
237 // domain has a gap by 1, the FIFO not empty status is raised.
238 //
239 // At this time, the logic just sent the read request to the SRAM. The data
240 // is not yet read. The `rvalid` asserts when it receives data from the
241 // SRAM.
242 //
243 // So, if the consumer reads data at the same cycle when notempty status is
244 // raised, it reads incorrect data.
245 1/1 assign r_notempty_o = rvalid_o;
Tests: T1 T2 T3
246
247 1/1 assign rsram_ack = r_sram_req_o && r_sram_gnt_i;
Tests: T1 T2 T3
248 1/1 assign rfifo_ack = rvalid_o && rready_i;
Tests: T1 T2 T3
249
250 // SRAM Write Request
251 1/1 assign w_sram_req_o = wvalid_i && !w_full;
Tests: T1 T2 T3
252 1/1 assign wready_o = !w_full && w_sram_gnt_i;
Tests: T1 T2 T3
253 assign w_sram_write_o = 1'b 1; // Always write
254 1/1 assign w_sram_addr_o = SramBaseAddr + SramAw'(w_wptr_v);
Tests: T1 T2 T3
255
256 1/1 assign w_sram_wdata_o = SramDw'(wdata_i);
Tests: T1 T2 T3
257 assign w_sram_wmask_o = SramDw'({Width{1'b1}});
258
259 logic unused_w_sram;
260 1/1 assign unused_w_sram = ^{w_sram_rvalid_i, w_sram_rdata_i, w_sram_rerror_i};
Tests: T1 T2 T3
261
262 // SRAM Read Request
263 // Request Scenario (!r_empty):
264 // - storage empty: Send request if
265 // !r_sram_rvalid_i || (rfifo_ack && r_sram_rvalid_i);
266 // - storage !empty: depends on the rfifo_ack:
267 // - r_rptr_inc: Can request more
268 // - !r_rptr_inc: Can't request
269 always_comb begin : r_sram_req
270 1/1 r_sram_req_o = 1'b 0;
Tests: T1 T2 T3
271 // Karnough Map (!empty): sram_req
272 // {sram_rv, rfifo_ack} | 00 | 01 | 11 | 10
273 // ----------------------------------------------------------
274 // stored | 0 | 1 | impossible | 1 | 0
275 // | 1 | 0 | 1 | X | impossible
276 //
277 // req_o = r_ptr_inc || (!stored && !r_sram_rvalid_i)
278
279 1/1 if (stored) begin
Tests: T1 T2 T3
280 // storage has data. depends on rfifo_ack
281 // rfifo_ack can be replaced to rready_i as `rvalid_o` is 1
282 1/1 r_sram_req_o = !r_sramrptr_empty && rfifo_ack;
Tests: T44 T42 T32
283 end else begin
284 // storage has no data.
285 // Can send request only when the reader accept the request or no
286 // previous request sent out.
287 1/1 r_sram_req_o = !r_sramrptr_empty && !(r_sram_rvalid_i ^ rfifo_ack);
Tests: T1 T2 T3
288 end
289 end : r_sram_req
290
291 1/1 assign rvalid_o = stored || r_sram_rvalid_i;
Tests: T1 T2 T3
292 assign r_sram_write_o = 1'b 0; // always read
293 assign r_sram_wdata_o = '0;
294 assign r_sram_wmask_o = '0;
295
296 // Send SRAM request with sram read pointer.
297 1/1 assign r_sram_addr_o = SramBaseAddr + SramAw'(r_sram_rptr[0+:PtrVW]);
Tests: T1 T2 T3
298
299 1/1 assign rdata_d = (r_sram_rvalid_i) ? r_sram_rdata_i[0+:Width] : Width'(0);
Tests: T1 T2 T3
300
301 1/1 assign rdata_o = (stored) ? rdata_q : rdata_d;
Tests: T1 T2 T3
302
303 logic unused_rsram;
304 1/1 assign unused_rsram = ^{r_sram_rerror_i};
Tests: T1 T2 T3
305
306 if (Width < SramDw) begin : g_unused_rdata
307 logic unused_rdata;
308 assign unused_rdata = ^r_sram_rdata_i[SramDw-1:Width];
309 end : g_unused_rdata
310
311 // read clock domain rdata storage
312 logic store_en;
313
314 // Karnough Map (r_sram_rvalid_i):
315 // rfifo_ack | 0 | 1 |
316 // ---------------------
317 // stored 0 | 1 | 0 |
318 // 1 | 0 | 1 |
319 //
320 // stored = s.r.v && XNOR(stored, rptr_inc)
321 1/1 assign store_en = r_sram_rvalid_i && !(stored ^ rfifo_ack);
Tests: T1 T2 T3
322
323 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
324 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
325 1/1 stored <= 1'b 0;
Tests: T1 T2 T3
326 1/1 rdata_q <= Width'(0);
Tests: T1 T2 T3
327 1/1 end else if (store_en) begin
Tests: T1 T2 T3
328 1/1 stored <= 1'b 1;
Tests: T44 T42 T32
329 1/1 rdata_q <= rdata_d;
Tests: T44 T42 T32
330 1/1 end else if (!r_sram_rvalid_i && rfifo_ack) begin
Tests: T1 T2 T3
331 // No request sent, host reads the data
332 1/1 stored <= 1'b 0;
Tests: T44 T42 T32
333 1/1 rdata_q <= Width'(0);
Tests: T44 T42 T32
334 end
MISSING_ELSE
335 end
336
337 //////////////
338 // Function //
339 //////////////
340
341 // dec2gray / gray2dec copied from prim_fifo_async.sv
342 function automatic [PtrW-1:0] dec2gray(input logic [PtrW-1:0] decval);
343 logic [PtrW-1:0] decval_sub;
344 logic [PtrW-1:0] decval_in;
345 logic unused_decval_msb;
346
347 1/1 decval_sub = (PtrW)'(Depth) - {1'b0, decval[PtrW-2:0]} - 1'b1;
Tests: T1 T2 T3
348
349 1/1 decval_in = decval[PtrW-1] ? decval_sub : decval;
Tests: T1 T2 T3
350
351 // We do not care about the MSB, hence we mask it out
352 1/1 unused_decval_msb = decval_in[PtrW-1];
Tests: T1 T2 T3
353 1/1 decval_in[PtrW-1] = 1'b0;
Tests: T1 T2 T3
354
355 // Perform the XOR conversion
356 1/1 dec2gray = decval_in;
Tests: T1 T2 T3
357 1/1 dec2gray ^= (decval_in >> 1);
Tests: T1 T2 T3
358
359 // Override the MSB
360 1/1 dec2gray[PtrW-1] = decval[PtrW-1];
Tests: T1 T2 T3
361 endfunction
362
363 // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
364 function automatic [PtrW-1:0] gray2dec(input logic [PtrW-1:0] grayval);
365 logic [PtrW-1:0] dec_tmp, dec_tmp_sub;
366 logic unused_decsub_msb;
367
368 1/1 dec_tmp = '0;
Tests: T1 T2 T3
369 1/1 for (int i = PtrW-2; i >= 0; i--) begin
Tests: T1 T2 T3
370 1/1 dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
Tests: T1 T2 T3
371 end
372 1/1 dec_tmp_sub = (PtrW)'(Depth) - dec_tmp - 1'b1;
Tests: T1 T2 T3
373 1/1 if (grayval[PtrW-1]) begin
Tests: T1 T2 T3
374 1/1 gray2dec = dec_tmp_sub;
Tests: T86 T39 T40
375 // Override MSB
376 1/1 gray2dec[PtrW-1] = 1'b1;
Tests: T86 T39 T40
377 1/1 unused_decsub_msb = dec_tmp_sub[PtrW-1];
Tests: T86 T39 T40
378 end else begin
379 1/1 gray2dec = dec_tmp;
Tests: T1 T2 T3
Cond Coverage for Module :
prim_fifo_async_sram_adapter ( parameter Width=16,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=960,DepthW=5,PtrVW=4,PtrW=5 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 68 | 51 | 75.00 |
| Logical | 68 | 51 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 121
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 153
EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T50,T85,T65 |
| 1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (w_wptr_p == w_rptr_p)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T50,T85,T65 |
| 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (r_wptr_p == r_rptr_p)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (r_wptr == r_sram_rptr)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 218
EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 219
EXPRESSION (r_wptr == r_rptr_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (r_sram_req_o && r_sram_gnt_i)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 248
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 251
EXPRESSION (wvalid_i && ((!w_full)))
----1--- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 252
EXPRESSION (((!w_full)) && w_sram_gnt_i)
-----1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 282
EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
----------1---------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 287
EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
----------1---------- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 287
SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 287
SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
-------1------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Not Covered | |
LINE 291
EXPRESSION (stored || r_sram_rvalid_i)
---1-- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Covered | T44,T42,T32 |
LINE 299
EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (16'(0)))
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 301
EXPRESSION (stored ? rdata_q : rdata_d)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 321
EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
-------1------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 321
SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 321
SUB-EXPRESSION (stored ^ rfifo_ack)
---1-- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 330
EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
----------1--------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 349
EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T50,T85,T65 |
LINE 370
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Covered | T42,T32,T49 |
| 1 | 1 | Covered | T44,T42,T32 |
Cond Coverage for Module :
prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=976,DepthW=5,PtrVW=4,PtrW=5 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 68 | 51 | 75.00 |
| Logical | 68 | 51 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 121
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 153
EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T86,T39,T40 |
| 1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (w_wptr_p == w_rptr_p)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T86,T39,T40 |
| 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (r_wptr_p == r_rptr_p)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (r_wptr == r_sram_rptr)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 218
EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 219
EXPRESSION (r_wptr == r_rptr_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (r_sram_req_o && r_sram_gnt_i)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 248
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 251
EXPRESSION (wvalid_i && ((!w_full)))
----1--- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 252
EXPRESSION (((!w_full)) && w_sram_gnt_i)
-----1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 282
EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
----------1---------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 287
EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
----------1---------- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 287
SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 287
SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
-------1------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Not Covered | |
LINE 291
EXPRESSION (stored || r_sram_rvalid_i)
---1-- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Covered | T44,T42,T32 |
LINE 299
EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (32'(0)))
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 301
EXPRESSION (stored ? rdata_q : rdata_d)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 321
EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
-------1------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 321
SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 321
SUB-EXPRESSION (stored ^ rfifo_ack)
---1-- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 330
EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
----------1--------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 349
EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T86,T39,T87 |
LINE 370
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Covered | T42,T32,T49 |
| 1 | 1 | Covered | T44,T42,T32 |
Branch Coverage for Module :
prim_fifo_async_sram_adapter
| Line No. | Total | Covered | Percent |
| Branches |
|
27 |
27 |
100.00 |
| TERNARY |
153 |
2 |
2 |
100.00 |
| TERNARY |
195 |
2 |
2 |
100.00 |
| TERNARY |
299 |
2 |
2 |
100.00 |
| TERNARY |
301 |
2 |
2 |
100.00 |
| IF |
126 |
3 |
3 |
100.00 |
| IF |
168 |
3 |
3 |
100.00 |
| IF |
204 |
3 |
3 |
100.00 |
| IF |
279 |
2 |
2 |
100.00 |
| IF |
324 |
4 |
4 |
100.00 |
| TERNARY |
349 |
2 |
2 |
100.00 |
| IF |
373 |
2 |
2 |
100.00 |
153 assign wdepth_o = (w_wptr_p == w_rptr_p)
154 ? DepthW'(w_wptr_v - w_rptr_v)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T50,T85,T65 |
195 assign rdepth_o = (r_wptr_p == r_rptr_p)
196 ? DepthW'(r_wptr_v - r_rptr_v)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T50,T85,T65 |
299 assign rdata_d = (r_sram_rvalid_i) ? r_sram_rdata_i[0+:Width] : Width'(0);
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
301 assign rdata_o = (stored) ? rdata_q : rdata_d;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
126 if (!rst_wr_ni) begin
-1-
127 w_wptr_q <= PtrW'(0);
==>
128 w_wptr_gray_q <= PtrW'(0);
129 end else if (w_wptr_inc) begin
-2-
130 w_wptr_q <= w_wptr_d;
==>
131 w_wptr_gray_q <= w_wptr_gray_d;
132 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T4,T5,T6 |
168 if (!rst_rd_ni) begin
-1-
169 r_rptr_q <= PtrW'(0);
==>
170 r_rptr_gray_q <= PtrW'(0);
171 end else if (r_rptr_inc) begin
-2-
172 r_rptr_q <= r_rptr_d;
==>
173 r_rptr_gray_q <= r_rptr_gray_d;
174 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
204 if (!rst_rd_ni) begin
-1-
205 r_sram_rptr <= PtrW'(0);
==>
206 end else if (r_sram_rptr_inc) begin
-2-
207 r_sram_rptr <= r_sram_rptr + PtrW'(1);
==>
208 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
279 if (stored) begin
-1-
280 // storage has data. depends on rfifo_ack
281 // rfifo_ack can be replaced to rready_i as `rvalid_o` is 1
282 r_sram_req_o = !r_sramrptr_empty && rfifo_ack;
==>
283 end else begin
284 // storage has no data.
285 // Can send request only when the reader accept the request or no
286 // previous request sent out.
287 r_sram_req_o = !r_sramrptr_empty && !(r_sram_rvalid_i ^ rfifo_ack);
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
324 if (!rst_rd_ni) begin
-1-
325 stored <= 1'b 0;
==>
326 rdata_q <= Width'(0);
327 end else if (store_en) begin
-2-
328 stored <= 1'b 1;
==>
329 rdata_q <= rdata_d;
330 end else if (!r_sram_rvalid_i && rfifo_ack) begin
-3-
331 // No request sent, host reads the data
332 stored <= 1'b 0;
==>
333 rdata_q <= Width'(0);
334 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T44,T42,T32 |
| 0 |
0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
349 decval_in = decval[PtrW-1] ? decval_sub : decval;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T50,T85,T65 |
| 0 |
Covered |
T1,T2,T3 |
373 if (grayval[PtrW-1]) begin
-1-
374 gray2dec = dec_tmp_sub;
==>
375 // Override MSB
376 gray2dec[PtrW-1] = 1'b1;
377 unused_decsub_msb = dec_tmp_sub[PtrW-1];
378 end else begin
379 gray2dec = dec_tmp;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T50,T85,T65 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_async_sram_adapter
Assertion Details
MinDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1950 |
1950 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
NoRAckInEmpty_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
914938806 |
4187 |
0 |
0 |
| T21 |
7660 |
0 |
0 |
0 |
| T22 |
8822 |
0 |
0 |
0 |
| T26 |
147346 |
0 |
0 |
0 |
| T27 |
3306 |
0 |
0 |
0 |
| T28 |
1543788 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
329196 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
852020 |
4 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
74454 |
0 |
0 |
0 |
| T52 |
460494 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
| T81 |
2694 |
0 |
0 |
0 |
NoWAckInFull_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
302426034 |
4187 |
0 |
0 |
| T26 |
130578 |
0 |
0 |
0 |
| T28 |
200442 |
0 |
0 |
0 |
| T29 |
206720 |
0 |
0 |
0 |
| T30 |
450914 |
0 |
0 |
0 |
| T31 |
493240 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
51272 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
207164 |
4 |
0 |
0 |
| T45 |
21050 |
0 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
68242 |
0 |
0 |
0 |
| T52 |
113520 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1950 |
1950 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
RSramRvalidOneCycle_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
914938806 |
4187 |
0 |
0 |
| T21 |
7660 |
0 |
0 |
0 |
| T22 |
8822 |
0 |
0 |
0 |
| T26 |
147346 |
0 |
0 |
0 |
| T27 |
3306 |
0 |
0 |
0 |
| T28 |
1543788 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
329196 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
852020 |
4 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
74454 |
0 |
0 |
0 |
| T52 |
460494 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
| T81 |
2694 |
0 |
0 |
0 |
RptrGrayOneBitAtATime_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
914938806 |
4187 |
0 |
0 |
| T21 |
7660 |
0 |
0 |
0 |
| T22 |
8822 |
0 |
0 |
0 |
| T26 |
147346 |
0 |
0 |
0 |
| T27 |
3306 |
0 |
0 |
0 |
| T28 |
1543788 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
329196 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
852020 |
4 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
74454 |
0 |
0 |
0 |
| T52 |
460494 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
| T81 |
2694 |
0 |
0 |
0 |
RptrIncDataValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
914938806 |
4187 |
0 |
0 |
| T21 |
7660 |
0 |
0 |
0 |
| T22 |
8822 |
0 |
0 |
0 |
| T26 |
147346 |
0 |
0 |
0 |
| T27 |
3306 |
0 |
0 |
0 |
| T28 |
1543788 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
329196 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
852020 |
4 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
74454 |
0 |
0 |
0 |
| T52 |
460494 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
| T81 |
2694 |
0 |
0 |
0 |
RptrIncrease_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
914938806 |
4187 |
0 |
0 |
| T21 |
7660 |
0 |
0 |
0 |
| T22 |
8822 |
0 |
0 |
0 |
| T26 |
147346 |
0 |
0 |
0 |
| T27 |
3306 |
0 |
0 |
0 |
| T28 |
1543788 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
329196 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
852020 |
4 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
74454 |
0 |
0 |
0 |
| T52 |
460494 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
| T81 |
2694 |
0 |
0 |
0 |
SramRvalid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
914938806 |
4187 |
0 |
0 |
| T21 |
7660 |
0 |
0 |
0 |
| T22 |
8822 |
0 |
0 |
0 |
| T26 |
147346 |
0 |
0 |
0 |
| T27 |
3306 |
0 |
0 |
0 |
| T28 |
1543788 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
329196 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
852020 |
4 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
74454 |
0 |
0 |
0 |
| T52 |
460494 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
| T81 |
2694 |
0 |
0 |
0 |
WSramRvalid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
302426034 |
302426034 |
0 |
0 |
| T4 |
3376 |
3376 |
0 |
0 |
| T5 |
1440 |
1440 |
0 |
0 |
| T6 |
24542 |
24542 |
0 |
0 |
| T7 |
25866 |
25866 |
0 |
0 |
| T9 |
78240 |
78240 |
0 |
0 |
| T11 |
44486 |
44486 |
0 |
0 |
| T13 |
45726 |
45726 |
0 |
0 |
| T14 |
29366 |
29366 |
0 |
0 |
| T15 |
432 |
432 |
0 |
0 |
| T16 |
2256 |
2256 |
0 |
0 |
WidthMatch_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1950 |
1950 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
WptrGrayOneBitAtATime_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
302426034 |
4187 |
0 |
0 |
| T26 |
130578 |
0 |
0 |
0 |
| T28 |
200442 |
0 |
0 |
0 |
| T29 |
206720 |
0 |
0 |
0 |
| T30 |
450914 |
0 |
0 |
0 |
| T31 |
493240 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
51272 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
207164 |
4 |
0 |
0 |
| T45 |
21050 |
0 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
68242 |
0 |
0 |
0 |
| T52 |
113520 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
WptrIncrease_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
302426034 |
4187 |
0 |
0 |
| T26 |
130578 |
0 |
0 |
0 |
| T28 |
200442 |
0 |
0 |
0 |
| T29 |
206720 |
0 |
0 |
0 |
| T30 |
450914 |
0 |
0 |
0 |
| T31 |
493240 |
0 |
0 |
0 |
| T32 |
0 |
18 |
0 |
0 |
| T35 |
0 |
6 |
0 |
0 |
| T38 |
51272 |
0 |
0 |
0 |
| T42 |
0 |
6 |
0 |
0 |
| T44 |
207164 |
4 |
0 |
0 |
| T45 |
21050 |
0 |
0 |
0 |
| T47 |
0 |
12 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T49 |
0 |
12 |
0 |
0 |
| T51 |
68242 |
0 |
0 |
0 |
| T52 |
113520 |
0 |
0 |
0 |
| T58 |
0 |
7 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T77 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 86 | 86 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
| ALWAYS | 168 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| ALWAYS | 204 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 248 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
| ALWAYS | 270 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
| ALWAYS | 324 | 9 | 9 | 100.00 |
| ROUTINE | 347 | 7 | 7 | 100.00 |
| ROUTINE | 368 | 9 | 9 | 100.00 |
120 // Begin: Write pointer sync to read clock ========================
121 1/1 assign w_wptr_inc = wvalid_i & wready_o;
Tests: T1 T2 T3
122
123 1/1 assign w_wptr_d = w_wptr_q + PtrW'(1);
Tests: T1 T2 T3
124
125 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
126 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
127 1/1 w_wptr_q <= PtrW'(0);
Tests: T1 T2 T3
128 1/1 w_wptr_gray_q <= PtrW'(0);
Tests: T1 T2 T3
129 1/1 end else if (w_wptr_inc) begin
Tests: T4 T5 T6
130 1/1 w_wptr_q <= w_wptr_d;
Tests: T44 T42 T32
131 1/1 w_wptr_gray_q <= w_wptr_gray_d;
Tests: T44 T42 T32
132 end
MISSING_ELSE
133 end
134
135 1/1 assign w_wptr_v = w_wptr_q[0+:PtrVW];
Tests: T1 T2 T3
136 1/1 assign w_wptr_p = w_wptr_q[PtrW-1];
Tests: T1 T2 T3
137
138 1/1 assign w_wptr_gray_d = dec2gray(w_wptr_d);
Tests: T1 T2 T3
139
140 prim_flop_2sync #(
141 .Width (PtrW)
142 ) u_sync_wptr_gray (
143 .clk_i (clk_rd_i),
144 .rst_ni (rst_rd_ni),
145 .d_i (w_wptr_gray_q),
146 .q_o (r_wptr_gray)
147 );
148
149 1/1 assign r_wptr = gray2dec(r_wptr_gray);
Tests: T1 T2 T3
150 1/1 assign r_wptr_p = r_wptr[PtrW-1];
Tests: T1 T2 T3
151 1/1 assign r_wptr_v = r_wptr[0+:PtrVW];
Tests: T1 T2 T3
152
153 1/1 assign wdepth_o = (w_wptr_p == w_rptr_p)
Tests: T1 T2 T3
154 ? DepthW'(w_wptr_v - w_rptr_v)
155 : DepthW'({1'b1, w_wptr_v} - {1'b 0, w_rptr_v});
156 // End: Write pointer sync to read clock ------------------------
157
158 // Begin: Read pointer sync to write clock ========================
159 //assign r_rptr_inc = rvalid_o & rready_i;
160 //assign r_rptr_inc = r_sram_req_o && r_sram_gnt_i;
161 // Increase the read pointer (crossing the clock domain) only when the
162 // reader acked.
163 1/1 assign r_rptr_inc = rfifo_ack;
Tests: T44 T42 T32
164
165 1/1 assign r_rptr_d = r_rptr_q + PtrW'(1);
Tests: T1 T2 T3
166
167 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
168 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
169 1/1 r_rptr_q <= PtrW'(0);
Tests: T1 T2 T3
170 1/1 r_rptr_gray_q <= PtrW'(0);
Tests: T1 T2 T3
171 1/1 end else if (r_rptr_inc) begin
Tests: T1 T2 T3
172 1/1 r_rptr_q <= r_rptr_d;
Tests: T44 T42 T32
173 1/1 r_rptr_gray_q <= r_rptr_gray_d;
Tests: T44 T42 T32
174 end
MISSING_ELSE
175 end
176
177 1/1 assign r_rptr_v = r_rptr_q[0+:PtrVW];
Tests: T1 T2 T3
178 1/1 assign r_rptr_p = r_rptr_q[PtrW-1];
Tests: T1 T2 T3
179
180 1/1 assign r_rptr_gray_d = dec2gray(r_rptr_d);
Tests: T1 T2 T3
181
182 prim_flop_2sync #(
183 .Width (PtrW)
184 ) u_sync_rptr_gray (
185 .clk_i (clk_wr_i),
186 .rst_ni (rst_wr_ni),
187 .d_i (r_rptr_gray_q),
188 .q_o (w_rptr_gray)
189 );
190
191 1/1 assign w_rptr = gray2dec(w_rptr_gray);
Tests: T1 T2 T3
192 1/1 assign w_rptr_p = w_rptr[PtrW-1];
Tests: T1 T2 T3
193 1/1 assign w_rptr_v = w_rptr[0+:PtrVW];
Tests: T1 T2 T3
194
195 1/1 assign rdepth_o = (r_wptr_p == r_rptr_p)
Tests: T1 T2 T3
196 ? DepthW'(r_wptr_v - r_rptr_v)
197 : DepthW'({1'b1, r_wptr_v} - {1'b 0, r_rptr_v});
198 // End: Read pointer sync to write clock ------------------------
199
200 // Begin: SRAM Read pointer
201 1/1 assign r_sram_rptr_inc = rsram_ack;
Tests: T1 T2 T3
202
203 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
204 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
205 1/1 r_sram_rptr <= PtrW'(0);
Tests: T1 T2 T3
206 1/1 end else if (r_sram_rptr_inc) begin
Tests: T1 T2 T3
207 1/1 r_sram_rptr <= r_sram_rptr + PtrW'(1);
Tests: T44 T42 T32
208 end
MISSING_ELSE
209 end
210
211 1/1 assign r_sramrptr_empty = (r_wptr == r_sram_rptr);
Tests: T1 T2 T3
212 // End: SRAM Read pointer
213
214 // Full/ Empty
215 // Lint complains PtrW'(1) << (PtrW-1). So changed as below
216 localparam logic [PtrW-1:0] XorMask = {1'b 1, {PtrW-1{1'b0}}};
217 1/1 assign w_full = (w_wptr_q == (w_rptr ^ XorMask));
Tests: T1 T2 T3
218 1/1 assign r_full = (r_wptr == (r_rptr_q ^ XorMask));
Tests: T1 T2 T3
219 1/1 assign r_empty = (r_wptr == r_rptr_q);
Tests: T1 T2 T3
220
221 logic unused_r_empty;
222 1/1 assign unused_r_empty = r_empty;
Tests: T1 T2 T3
223
224 1/1 assign r_full_o = r_full;
Tests: T1 T2 T3
225 1/1 assign w_full_o = w_full;
Tests: T1 T2 T3
226
227 // The notempty status !(wptr == rptr) assert one clock earlier than the
228 // actual `rvalid` signals.
229 //
230 // The reason is due to the SRAM read latency. The module uses SRAM FIFO
231 // interface. When the logic in producer domain pushes entries, the pointer
232 // is increased. This triggers the FIFO logic in the consumer clock domain
233 // fetches data from SRAM.
234 //
235 // The pointer crosses the clock boundary. It takes usually two cycles (in
236 // the consumer side). Then, as the read and write pointer in the read clock
237 // domain has a gap by 1, the FIFO not empty status is raised.
238 //
239 // At this time, the logic just sent the read request to the SRAM. The data
240 // is not yet read. The `rvalid` asserts when it receives data from the
241 // SRAM.
242 //
243 // So, if the consumer reads data at the same cycle when notempty status is
244 // raised, it reads incorrect data.
245 1/1 assign r_notempty_o = rvalid_o;
Tests: T1 T2 T3
246
247 1/1 assign rsram_ack = r_sram_req_o && r_sram_gnt_i;
Tests: T1 T2 T3
248 1/1 assign rfifo_ack = rvalid_o && rready_i;
Tests: T1 T2 T3
249
250 // SRAM Write Request
251 1/1 assign w_sram_req_o = wvalid_i && !w_full;
Tests: T1 T2 T3
252 1/1 assign wready_o = !w_full && w_sram_gnt_i;
Tests: T1 T2 T3
253 assign w_sram_write_o = 1'b 1; // Always write
254 1/1 assign w_sram_addr_o = SramBaseAddr + SramAw'(w_wptr_v);
Tests: T1 T2 T3
255
256 1/1 assign w_sram_wdata_o = SramDw'(wdata_i);
Tests: T1 T2 T3
257 assign w_sram_wmask_o = SramDw'({Width{1'b1}});
258
259 logic unused_w_sram;
260 1/1 assign unused_w_sram = ^{w_sram_rvalid_i, w_sram_rdata_i, w_sram_rerror_i};
Tests: T1 T2 T3
261
262 // SRAM Read Request
263 // Request Scenario (!r_empty):
264 // - storage empty: Send request if
265 // !r_sram_rvalid_i || (rfifo_ack && r_sram_rvalid_i);
266 // - storage !empty: depends on the rfifo_ack:
267 // - r_rptr_inc: Can request more
268 // - !r_rptr_inc: Can't request
269 always_comb begin : r_sram_req
270 1/1 r_sram_req_o = 1'b 0;
Tests: T1 T2 T3
271 // Karnough Map (!empty): sram_req
272 // {sram_rv, rfifo_ack} | 00 | 01 | 11 | 10
273 // ----------------------------------------------------------
274 // stored | 0 | 1 | impossible | 1 | 0
275 // | 1 | 0 | 1 | X | impossible
276 //
277 // req_o = r_ptr_inc || (!stored && !r_sram_rvalid_i)
278
279 1/1 if (stored) begin
Tests: T1 T2 T3
280 // storage has data. depends on rfifo_ack
281 // rfifo_ack can be replaced to rready_i as `rvalid_o` is 1
282 1/1 r_sram_req_o = !r_sramrptr_empty && rfifo_ack;
Tests: T44 T42 T32
283 end else begin
284 // storage has no data.
285 // Can send request only when the reader accept the request or no
286 // previous request sent out.
287 1/1 r_sram_req_o = !r_sramrptr_empty && !(r_sram_rvalid_i ^ rfifo_ack);
Tests: T1 T2 T3
288 end
289 end : r_sram_req
290
291 1/1 assign rvalid_o = stored || r_sram_rvalid_i;
Tests: T1 T2 T3
292 assign r_sram_write_o = 1'b 0; // always read
293 assign r_sram_wdata_o = '0;
294 assign r_sram_wmask_o = '0;
295
296 // Send SRAM request with sram read pointer.
297 1/1 assign r_sram_addr_o = SramBaseAddr + SramAw'(r_sram_rptr[0+:PtrVW]);
Tests: T1 T2 T3
298
299 1/1 assign rdata_d = (r_sram_rvalid_i) ? r_sram_rdata_i[0+:Width] : Width'(0);
Tests: T1 T2 T3
300
301 1/1 assign rdata_o = (stored) ? rdata_q : rdata_d;
Tests: T1 T2 T3
302
303 logic unused_rsram;
304 1/1 assign unused_rsram = ^{r_sram_rerror_i};
Tests: T1 T2 T3
305
306 if (Width < SramDw) begin : g_unused_rdata
307 logic unused_rdata;
308 1/1 assign unused_rdata = ^r_sram_rdata_i[SramDw-1:Width];
Tests: T2 T4 T25
309 end : g_unused_rdata
310
311 // read clock domain rdata storage
312 logic store_en;
313
314 // Karnough Map (r_sram_rvalid_i):
315 // rfifo_ack | 0 | 1 |
316 // ---------------------
317 // stored 0 | 1 | 0 |
318 // 1 | 0 | 1 |
319 //
320 // stored = s.r.v && XNOR(stored, rptr_inc)
321 1/1 assign store_en = r_sram_rvalid_i && !(stored ^ rfifo_ack);
Tests: T1 T2 T3
322
323 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
324 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
325 1/1 stored <= 1'b 0;
Tests: T1 T2 T3
326 1/1 rdata_q <= Width'(0);
Tests: T1 T2 T3
327 1/1 end else if (store_en) begin
Tests: T1 T2 T3
328 1/1 stored <= 1'b 1;
Tests: T44 T42 T32
329 1/1 rdata_q <= rdata_d;
Tests: T44 T42 T32
330 1/1 end else if (!r_sram_rvalid_i && rfifo_ack) begin
Tests: T1 T2 T3
331 // No request sent, host reads the data
332 1/1 stored <= 1'b 0;
Tests: T44 T42 T32
333 1/1 rdata_q <= Width'(0);
Tests: T44 T42 T32
334 end
MISSING_ELSE
335 end
336
337 //////////////
338 // Function //
339 //////////////
340
341 // dec2gray / gray2dec copied from prim_fifo_async.sv
342 function automatic [PtrW-1:0] dec2gray(input logic [PtrW-1:0] decval);
343 logic [PtrW-1:0] decval_sub;
344 logic [PtrW-1:0] decval_in;
345 logic unused_decval_msb;
346
347 1/1 decval_sub = (PtrW)'(Depth) - {1'b0, decval[PtrW-2:0]} - 1'b1;
Tests: T1 T2 T3
348
349 1/1 decval_in = decval[PtrW-1] ? decval_sub : decval;
Tests: T1 T2 T3
350
351 // We do not care about the MSB, hence we mask it out
352 1/1 unused_decval_msb = decval_in[PtrW-1];
Tests: T1 T2 T3
353 1/1 decval_in[PtrW-1] = 1'b0;
Tests: T1 T2 T3
354
355 // Perform the XOR conversion
356 1/1 dec2gray = decval_in;
Tests: T1 T2 T3
357 1/1 dec2gray ^= (decval_in >> 1);
Tests: T1 T2 T3
358
359 // Override the MSB
360 1/1 dec2gray[PtrW-1] = decval[PtrW-1];
Tests: T1 T2 T3
361 endfunction
362
363 // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
364 function automatic [PtrW-1:0] gray2dec(input logic [PtrW-1:0] grayval);
365 logic [PtrW-1:0] dec_tmp, dec_tmp_sub;
366 logic unused_decsub_msb;
367
368 1/1 dec_tmp = '0;
Tests: T1 T2 T3
369 1/1 for (int i = PtrW-2; i >= 0; i--) begin
Tests: T1 T2 T3
370 1/1 dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
Tests: T1 T2 T3
371 end
372 1/1 dec_tmp_sub = (PtrW)'(Depth) - dec_tmp - 1'b1;
Tests: T1 T2 T3
373 1/1 if (grayval[PtrW-1]) begin
Tests: T1 T2 T3
374 1/1 gray2dec = dec_tmp_sub;
Tests: T50 T85 T65
375 // Override MSB
376 1/1 gray2dec[PtrW-1] = 1'b1;
Tests: T50 T85 T65
377 1/1 unused_decsub_msb = dec_tmp_sub[PtrW-1];
Tests: T50 T85 T65
378 end else begin
379 1/1 gray2dec = dec_tmp;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_upload.u_cmdfifo
| Total | Covered | Percent |
|---|
| Conditions | 68 | 51 | 75.00 |
| Logical | 68 | 51 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 121
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 153
EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T50,T85,T65 |
| 1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (w_wptr_p == w_rptr_p)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T50,T85,T65 |
| 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (r_wptr_p == r_rptr_p)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (r_wptr == r_sram_rptr)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 218
EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 219
EXPRESSION (r_wptr == r_rptr_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (r_sram_req_o && r_sram_gnt_i)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 248
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 251
EXPRESSION (wvalid_i && ((!w_full)))
----1--- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 252
EXPRESSION (((!w_full)) && w_sram_gnt_i)
-----1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 282
EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
----------1---------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 287
EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
----------1---------- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 287
SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 287
SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
-------1------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Not Covered | |
LINE 291
EXPRESSION (stored || r_sram_rvalid_i)
---1-- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Covered | T44,T42,T32 |
LINE 299
EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (16'(0)))
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 301
EXPRESSION (stored ? rdata_q : rdata_d)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 321
EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
-------1------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 321
SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 321
SUB-EXPRESSION (stored ^ rfifo_ack)
---1-- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 330
EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
----------1--------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 349
EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T50,T85,T65 |
LINE 370
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Covered | T42,T32,T49 |
| 1 | 1 | Covered | T44,T42,T32 |
Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
27 |
27 |
100.00 |
| TERNARY |
153 |
2 |
2 |
100.00 |
| TERNARY |
195 |
2 |
2 |
100.00 |
| TERNARY |
299 |
2 |
2 |
100.00 |
| TERNARY |
301 |
2 |
2 |
100.00 |
| IF |
126 |
3 |
3 |
100.00 |
| IF |
168 |
3 |
3 |
100.00 |
| IF |
204 |
3 |
3 |
100.00 |
| IF |
279 |
2 |
2 |
100.00 |
| IF |
324 |
4 |
4 |
100.00 |
| TERNARY |
349 |
2 |
2 |
100.00 |
| IF |
373 |
2 |
2 |
100.00 |
153 assign wdepth_o = (w_wptr_p == w_rptr_p)
154 ? DepthW'(w_wptr_v - w_rptr_v)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T50,T85,T65 |
195 assign rdepth_o = (r_wptr_p == r_rptr_p)
196 ? DepthW'(r_wptr_v - r_rptr_v)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T50,T85,T65 |
299 assign rdata_d = (r_sram_rvalid_i) ? r_sram_rdata_i[0+:Width] : Width'(0);
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
301 assign rdata_o = (stored) ? rdata_q : rdata_d;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
126 if (!rst_wr_ni) begin
-1-
127 w_wptr_q <= PtrW'(0);
==>
128 w_wptr_gray_q <= PtrW'(0);
129 end else if (w_wptr_inc) begin
-2-
130 w_wptr_q <= w_wptr_d;
==>
131 w_wptr_gray_q <= w_wptr_gray_d;
132 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T4,T5,T6 |
168 if (!rst_rd_ni) begin
-1-
169 r_rptr_q <= PtrW'(0);
==>
170 r_rptr_gray_q <= PtrW'(0);
171 end else if (r_rptr_inc) begin
-2-
172 r_rptr_q <= r_rptr_d;
==>
173 r_rptr_gray_q <= r_rptr_gray_d;
174 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
204 if (!rst_rd_ni) begin
-1-
205 r_sram_rptr <= PtrW'(0);
==>
206 end else if (r_sram_rptr_inc) begin
-2-
207 r_sram_rptr <= r_sram_rptr + PtrW'(1);
==>
208 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
279 if (stored) begin
-1-
280 // storage has data. depends on rfifo_ack
281 // rfifo_ack can be replaced to rready_i as `rvalid_o` is 1
282 r_sram_req_o = !r_sramrptr_empty && rfifo_ack;
==>
283 end else begin
284 // storage has no data.
285 // Can send request only when the reader accept the request or no
286 // previous request sent out.
287 r_sram_req_o = !r_sramrptr_empty && !(r_sram_rvalid_i ^ rfifo_ack);
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
324 if (!rst_rd_ni) begin
-1-
325 stored <= 1'b 0;
==>
326 rdata_q <= Width'(0);
327 end else if (store_en) begin
-2-
328 stored <= 1'b 1;
==>
329 rdata_q <= rdata_d;
330 end else if (!r_sram_rvalid_i && rfifo_ack) begin
-3-
331 // No request sent, host reads the data
332 stored <= 1'b 0;
==>
333 rdata_q <= Width'(0);
334 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T44,T42,T32 |
| 0 |
0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
349 decval_in = decval[PtrW-1] ? decval_sub : decval;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T50,T85,T65 |
| 0 |
Covered |
T1,T2,T3 |
373 if (grayval[PtrW-1]) begin
-1-
374 gray2dec = dec_tmp_sub;
==>
375 // Override MSB
376 gray2dec[PtrW-1] = 1'b1;
377 unused_decsub_msb = dec_tmp_sub[PtrW-1];
378 end else begin
379 gray2dec = dec_tmp;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T50,T85,T65 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_upload.u_cmdfifo
Assertion Details
MinDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
975 |
975 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
NoRAckInEmpty_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
2390 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
NoWAckInFull_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151213017 |
2390 |
0 |
0 |
| T26 |
65289 |
0 |
0 |
0 |
| T28 |
100221 |
0 |
0 |
0 |
| T29 |
103360 |
0 |
0 |
0 |
| T30 |
225457 |
0 |
0 |
0 |
| T31 |
246620 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
25636 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
103582 |
2 |
0 |
0 |
| T45 |
10525 |
0 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
34121 |
0 |
0 |
0 |
| T52 |
56760 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
975 |
975 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
RSramRvalidOneCycle_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
2390 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
RptrGrayOneBitAtATime_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
2390 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
RptrIncDataValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
2390 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
RptrIncrease_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
2390 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
SramRvalid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
2390 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
WSramRvalid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151213017 |
151213017 |
0 |
0 |
| T4 |
1688 |
1688 |
0 |
0 |
| T5 |
720 |
720 |
0 |
0 |
| T6 |
12271 |
12271 |
0 |
0 |
| T7 |
12933 |
12933 |
0 |
0 |
| T9 |
39120 |
39120 |
0 |
0 |
| T11 |
22243 |
22243 |
0 |
0 |
| T13 |
22863 |
22863 |
0 |
0 |
| T14 |
14683 |
14683 |
0 |
0 |
| T15 |
216 |
216 |
0 |
0 |
| T16 |
1128 |
1128 |
0 |
0 |
WidthMatch_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
975 |
975 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
WptrGrayOneBitAtATime_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151213017 |
2390 |
0 |
0 |
| T26 |
65289 |
0 |
0 |
0 |
| T28 |
100221 |
0 |
0 |
0 |
| T29 |
103360 |
0 |
0 |
0 |
| T30 |
225457 |
0 |
0 |
0 |
| T31 |
246620 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
25636 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
103582 |
2 |
0 |
0 |
| T45 |
10525 |
0 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
34121 |
0 |
0 |
0 |
| T52 |
56760 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
WptrIncrease_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151213017 |
2390 |
0 |
0 |
| T26 |
65289 |
0 |
0 |
0 |
| T28 |
100221 |
0 |
0 |
0 |
| T29 |
103360 |
0 |
0 |
0 |
| T30 |
225457 |
0 |
0 |
0 |
| T31 |
246620 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T38 |
25636 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
103582 |
2 |
0 |
0 |
| T45 |
10525 |
0 |
0 |
0 |
| T47 |
0 |
8 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
34121 |
0 |
0 |
0 |
| T52 |
56760 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_addrfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 85 | 85 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
| ALWAYS | 168 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| ALWAYS | 204 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 248 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
| ALWAYS | 270 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
| ALWAYS | 324 | 9 | 9 | 100.00 |
| ROUTINE | 347 | 7 | 7 | 100.00 |
| ROUTINE | 368 | 9 | 9 | 100.00 |
120 // Begin: Write pointer sync to read clock ========================
121 1/1 assign w_wptr_inc = wvalid_i & wready_o;
Tests: T1 T2 T3
122
123 1/1 assign w_wptr_d = w_wptr_q + PtrW'(1);
Tests: T1 T2 T3
124
125 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
126 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
127 1/1 w_wptr_q <= PtrW'(0);
Tests: T1 T2 T3
128 1/1 w_wptr_gray_q <= PtrW'(0);
Tests: T1 T2 T3
129 1/1 end else if (w_wptr_inc) begin
Tests: T4 T5 T6
130 1/1 w_wptr_q <= w_wptr_d;
Tests: T44 T42 T32
131 1/1 w_wptr_gray_q <= w_wptr_gray_d;
Tests: T44 T42 T32
132 end
MISSING_ELSE
133 end
134
135 1/1 assign w_wptr_v = w_wptr_q[0+:PtrVW];
Tests: T1 T2 T3
136 1/1 assign w_wptr_p = w_wptr_q[PtrW-1];
Tests: T1 T2 T3
137
138 1/1 assign w_wptr_gray_d = dec2gray(w_wptr_d);
Tests: T1 T2 T3
139
140 prim_flop_2sync #(
141 .Width (PtrW)
142 ) u_sync_wptr_gray (
143 .clk_i (clk_rd_i),
144 .rst_ni (rst_rd_ni),
145 .d_i (w_wptr_gray_q),
146 .q_o (r_wptr_gray)
147 );
148
149 1/1 assign r_wptr = gray2dec(r_wptr_gray);
Tests: T1 T2 T3
150 1/1 assign r_wptr_p = r_wptr[PtrW-1];
Tests: T1 T2 T3
151 1/1 assign r_wptr_v = r_wptr[0+:PtrVW];
Tests: T1 T2 T3
152
153 1/1 assign wdepth_o = (w_wptr_p == w_rptr_p)
Tests: T1 T2 T3
154 ? DepthW'(w_wptr_v - w_rptr_v)
155 : DepthW'({1'b1, w_wptr_v} - {1'b 0, w_rptr_v});
156 // End: Write pointer sync to read clock ------------------------
157
158 // Begin: Read pointer sync to write clock ========================
159 //assign r_rptr_inc = rvalid_o & rready_i;
160 //assign r_rptr_inc = r_sram_req_o && r_sram_gnt_i;
161 // Increase the read pointer (crossing the clock domain) only when the
162 // reader acked.
163 1/1 assign r_rptr_inc = rfifo_ack;
Tests: T44 T42 T32
164
165 1/1 assign r_rptr_d = r_rptr_q + PtrW'(1);
Tests: T1 T2 T3
166
167 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
168 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
169 1/1 r_rptr_q <= PtrW'(0);
Tests: T1 T2 T3
170 1/1 r_rptr_gray_q <= PtrW'(0);
Tests: T1 T2 T3
171 1/1 end else if (r_rptr_inc) begin
Tests: T1 T2 T3
172 1/1 r_rptr_q <= r_rptr_d;
Tests: T44 T42 T32
173 1/1 r_rptr_gray_q <= r_rptr_gray_d;
Tests: T44 T42 T32
174 end
MISSING_ELSE
175 end
176
177 1/1 assign r_rptr_v = r_rptr_q[0+:PtrVW];
Tests: T1 T2 T3
178 1/1 assign r_rptr_p = r_rptr_q[PtrW-1];
Tests: T1 T2 T3
179
180 1/1 assign r_rptr_gray_d = dec2gray(r_rptr_d);
Tests: T1 T2 T3
181
182 prim_flop_2sync #(
183 .Width (PtrW)
184 ) u_sync_rptr_gray (
185 .clk_i (clk_wr_i),
186 .rst_ni (rst_wr_ni),
187 .d_i (r_rptr_gray_q),
188 .q_o (w_rptr_gray)
189 );
190
191 1/1 assign w_rptr = gray2dec(w_rptr_gray);
Tests: T1 T2 T3
192 1/1 assign w_rptr_p = w_rptr[PtrW-1];
Tests: T1 T2 T3
193 1/1 assign w_rptr_v = w_rptr[0+:PtrVW];
Tests: T1 T2 T3
194
195 1/1 assign rdepth_o = (r_wptr_p == r_rptr_p)
Tests: T1 T2 T3
196 ? DepthW'(r_wptr_v - r_rptr_v)
197 : DepthW'({1'b1, r_wptr_v} - {1'b 0, r_rptr_v});
198 // End: Read pointer sync to write clock ------------------------
199
200 // Begin: SRAM Read pointer
201 1/1 assign r_sram_rptr_inc = rsram_ack;
Tests: T1 T2 T3
202
203 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
204 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
205 1/1 r_sram_rptr <= PtrW'(0);
Tests: T1 T2 T3
206 1/1 end else if (r_sram_rptr_inc) begin
Tests: T1 T2 T3
207 1/1 r_sram_rptr <= r_sram_rptr + PtrW'(1);
Tests: T44 T42 T32
208 end
MISSING_ELSE
209 end
210
211 1/1 assign r_sramrptr_empty = (r_wptr == r_sram_rptr);
Tests: T1 T2 T3
212 // End: SRAM Read pointer
213
214 // Full/ Empty
215 // Lint complains PtrW'(1) << (PtrW-1). So changed as below
216 localparam logic [PtrW-1:0] XorMask = {1'b 1, {PtrW-1{1'b0}}};
217 1/1 assign w_full = (w_wptr_q == (w_rptr ^ XorMask));
Tests: T1 T2 T3
218 1/1 assign r_full = (r_wptr == (r_rptr_q ^ XorMask));
Tests: T1 T2 T3
219 1/1 assign r_empty = (r_wptr == r_rptr_q);
Tests: T1 T2 T3
220
221 logic unused_r_empty;
222 1/1 assign unused_r_empty = r_empty;
Tests: T1 T2 T3
223
224 1/1 assign r_full_o = r_full;
Tests: T1 T2 T3
225 1/1 assign w_full_o = w_full;
Tests: T1 T2 T3
226
227 // The notempty status !(wptr == rptr) assert one clock earlier than the
228 // actual `rvalid` signals.
229 //
230 // The reason is due to the SRAM read latency. The module uses SRAM FIFO
231 // interface. When the logic in producer domain pushes entries, the pointer
232 // is increased. This triggers the FIFO logic in the consumer clock domain
233 // fetches data from SRAM.
234 //
235 // The pointer crosses the clock boundary. It takes usually two cycles (in
236 // the consumer side). Then, as the read and write pointer in the read clock
237 // domain has a gap by 1, the FIFO not empty status is raised.
238 //
239 // At this time, the logic just sent the read request to the SRAM. The data
240 // is not yet read. The `rvalid` asserts when it receives data from the
241 // SRAM.
242 //
243 // So, if the consumer reads data at the same cycle when notempty status is
244 // raised, it reads incorrect data.
245 1/1 assign r_notempty_o = rvalid_o;
Tests: T1 T2 T3
246
247 1/1 assign rsram_ack = r_sram_req_o && r_sram_gnt_i;
Tests: T1 T2 T3
248 1/1 assign rfifo_ack = rvalid_o && rready_i;
Tests: T1 T2 T3
249
250 // SRAM Write Request
251 1/1 assign w_sram_req_o = wvalid_i && !w_full;
Tests: T1 T2 T3
252 1/1 assign wready_o = !w_full && w_sram_gnt_i;
Tests: T1 T2 T3
253 assign w_sram_write_o = 1'b 1; // Always write
254 1/1 assign w_sram_addr_o = SramBaseAddr + SramAw'(w_wptr_v);
Tests: T1 T2 T3
255
256 1/1 assign w_sram_wdata_o = SramDw'(wdata_i);
Tests: T1 T2 T3
257 assign w_sram_wmask_o = SramDw'({Width{1'b1}});
258
259 logic unused_w_sram;
260 1/1 assign unused_w_sram = ^{w_sram_rvalid_i, w_sram_rdata_i, w_sram_rerror_i};
Tests: T1 T2 T3
261
262 // SRAM Read Request
263 // Request Scenario (!r_empty):
264 // - storage empty: Send request if
265 // !r_sram_rvalid_i || (rfifo_ack && r_sram_rvalid_i);
266 // - storage !empty: depends on the rfifo_ack:
267 // - r_rptr_inc: Can request more
268 // - !r_rptr_inc: Can't request
269 always_comb begin : r_sram_req
270 1/1 r_sram_req_o = 1'b 0;
Tests: T1 T2 T3
271 // Karnough Map (!empty): sram_req
272 // {sram_rv, rfifo_ack} | 00 | 01 | 11 | 10
273 // ----------------------------------------------------------
274 // stored | 0 | 1 | impossible | 1 | 0
275 // | 1 | 0 | 1 | X | impossible
276 //
277 // req_o = r_ptr_inc || (!stored && !r_sram_rvalid_i)
278
279 1/1 if (stored) begin
Tests: T1 T2 T3
280 // storage has data. depends on rfifo_ack
281 // rfifo_ack can be replaced to rready_i as `rvalid_o` is 1
282 1/1 r_sram_req_o = !r_sramrptr_empty && rfifo_ack;
Tests: T44 T42 T32
283 end else begin
284 // storage has no data.
285 // Can send request only when the reader accept the request or no
286 // previous request sent out.
287 1/1 r_sram_req_o = !r_sramrptr_empty && !(r_sram_rvalid_i ^ rfifo_ack);
Tests: T1 T2 T3
288 end
289 end : r_sram_req
290
291 1/1 assign rvalid_o = stored || r_sram_rvalid_i;
Tests: T1 T2 T3
292 assign r_sram_write_o = 1'b 0; // always read
293 assign r_sram_wdata_o = '0;
294 assign r_sram_wmask_o = '0;
295
296 // Send SRAM request with sram read pointer.
297 1/1 assign r_sram_addr_o = SramBaseAddr + SramAw'(r_sram_rptr[0+:PtrVW]);
Tests: T1 T2 T3
298
299 1/1 assign rdata_d = (r_sram_rvalid_i) ? r_sram_rdata_i[0+:Width] : Width'(0);
Tests: T1 T2 T3
300
301 1/1 assign rdata_o = (stored) ? rdata_q : rdata_d;
Tests: T1 T2 T3
302
303 logic unused_rsram;
304 1/1 assign unused_rsram = ^{r_sram_rerror_i};
Tests: T1 T2 T3
305
306 if (Width < SramDw) begin : g_unused_rdata
307 logic unused_rdata;
308 assign unused_rdata = ^r_sram_rdata_i[SramDw-1:Width];
309 end : g_unused_rdata
310
311 // read clock domain rdata storage
312 logic store_en;
313
314 // Karnough Map (r_sram_rvalid_i):
315 // rfifo_ack | 0 | 1 |
316 // ---------------------
317 // stored 0 | 1 | 0 |
318 // 1 | 0 | 1 |
319 //
320 // stored = s.r.v && XNOR(stored, rptr_inc)
321 1/1 assign store_en = r_sram_rvalid_i && !(stored ^ rfifo_ack);
Tests: T1 T2 T3
322
323 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
324 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
325 1/1 stored <= 1'b 0;
Tests: T1 T2 T3
326 1/1 rdata_q <= Width'(0);
Tests: T1 T2 T3
327 1/1 end else if (store_en) begin
Tests: T1 T2 T3
328 1/1 stored <= 1'b 1;
Tests: T44 T42 T32
329 1/1 rdata_q <= rdata_d;
Tests: T44 T42 T32
330 1/1 end else if (!r_sram_rvalid_i && rfifo_ack) begin
Tests: T1 T2 T3
331 // No request sent, host reads the data
332 1/1 stored <= 1'b 0;
Tests: T44 T42 T32
333 1/1 rdata_q <= Width'(0);
Tests: T44 T42 T32
334 end
MISSING_ELSE
335 end
336
337 //////////////
338 // Function //
339 //////////////
340
341 // dec2gray / gray2dec copied from prim_fifo_async.sv
342 function automatic [PtrW-1:0] dec2gray(input logic [PtrW-1:0] decval);
343 logic [PtrW-1:0] decval_sub;
344 logic [PtrW-1:0] decval_in;
345 logic unused_decval_msb;
346
347 1/1 decval_sub = (PtrW)'(Depth) - {1'b0, decval[PtrW-2:0]} - 1'b1;
Tests: T1 T2 T3
348
349 1/1 decval_in = decval[PtrW-1] ? decval_sub : decval;
Tests: T1 T2 T3
350
351 // We do not care about the MSB, hence we mask it out
352 1/1 unused_decval_msb = decval_in[PtrW-1];
Tests: T1 T2 T3
353 1/1 decval_in[PtrW-1] = 1'b0;
Tests: T1 T2 T3
354
355 // Perform the XOR conversion
356 1/1 dec2gray = decval_in;
Tests: T1 T2 T3
357 1/1 dec2gray ^= (decval_in >> 1);
Tests: T1 T2 T3
358
359 // Override the MSB
360 1/1 dec2gray[PtrW-1] = decval[PtrW-1];
Tests: T1 T2 T3
361 endfunction
362
363 // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
364 function automatic [PtrW-1:0] gray2dec(input logic [PtrW-1:0] grayval);
365 logic [PtrW-1:0] dec_tmp, dec_tmp_sub;
366 logic unused_decsub_msb;
367
368 1/1 dec_tmp = '0;
Tests: T1 T2 T3
369 1/1 for (int i = PtrW-2; i >= 0; i--) begin
Tests: T1 T2 T3
370 1/1 dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
Tests: T1 T2 T3
371 end
372 1/1 dec_tmp_sub = (PtrW)'(Depth) - dec_tmp - 1'b1;
Tests: T1 T2 T3
373 1/1 if (grayval[PtrW-1]) begin
Tests: T1 T2 T3
374 1/1 gray2dec = dec_tmp_sub;
Tests: T86 T39 T40
375 // Override MSB
376 1/1 gray2dec[PtrW-1] = 1'b1;
Tests: T86 T39 T40
377 1/1 unused_decsub_msb = dec_tmp_sub[PtrW-1];
Tests: T86 T39 T40
378 end else begin
379 1/1 gray2dec = dec_tmp;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_upload.u_addrfifo
| Total | Covered | Percent |
|---|
| Conditions | 68 | 51 | 75.00 |
| Logical | 68 | 51 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 121
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 153
EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T86,T39,T40 |
| 1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (w_wptr_p == w_rptr_p)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T86,T39,T40 |
| 1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (r_wptr_p == r_rptr_p)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (r_wptr == r_sram_rptr)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 218
EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 219
EXPRESSION (r_wptr == r_rptr_q)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (r_sram_req_o && r_sram_gnt_i)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 248
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 251
EXPRESSION (wvalid_i && ((!w_full)))
----1--- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 252
EXPRESSION (((!w_full)) && w_sram_gnt_i)
-----1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 282
EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
----------1---------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 287
EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
----------1---------- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 287
SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 287
SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
-------1------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Not Covered | |
LINE 291
EXPRESSION (stored || r_sram_rvalid_i)
---1-- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Covered | T44,T42,T32 |
LINE 299
EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (32'(0)))
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 301
EXPRESSION (stored ? rdata_q : rdata_d)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 321
EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
-------1------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 321
SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T42,T32 |
LINE 321
SUB-EXPRESSION (stored ^ rfifo_ack)
---1-- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T44,T42,T32 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 330
EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
----------1--------- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T42,T32 |
LINE 349
EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T86,T39,T87 |
LINE 370
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T44,T42,T32 |
| 1 | 0 | Covered | T42,T32,T49 |
| 1 | 1 | Covered | T44,T42,T32 |
Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
27 |
27 |
100.00 |
| TERNARY |
153 |
2 |
2 |
100.00 |
| TERNARY |
195 |
2 |
2 |
100.00 |
| TERNARY |
299 |
2 |
2 |
100.00 |
| TERNARY |
301 |
2 |
2 |
100.00 |
| IF |
126 |
3 |
3 |
100.00 |
| IF |
168 |
3 |
3 |
100.00 |
| IF |
204 |
3 |
3 |
100.00 |
| IF |
279 |
2 |
2 |
100.00 |
| IF |
324 |
4 |
4 |
100.00 |
| TERNARY |
349 |
2 |
2 |
100.00 |
| IF |
373 |
2 |
2 |
100.00 |
153 assign wdepth_o = (w_wptr_p == w_rptr_p)
154 ? DepthW'(w_wptr_v - w_rptr_v)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T86,T39,T40 |
195 assign rdepth_o = (r_wptr_p == r_rptr_p)
196 ? DepthW'(r_wptr_v - r_rptr_v)
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T86,T39,T40 |
299 assign rdata_d = (r_sram_rvalid_i) ? r_sram_rdata_i[0+:Width] : Width'(0);
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
301 assign rdata_o = (stored) ? rdata_q : rdata_d;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
126 if (!rst_wr_ni) begin
-1-
127 w_wptr_q <= PtrW'(0);
==>
128 w_wptr_gray_q <= PtrW'(0);
129 end else if (w_wptr_inc) begin
-2-
130 w_wptr_q <= w_wptr_d;
==>
131 w_wptr_gray_q <= w_wptr_gray_d;
132 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T4,T5,T6 |
168 if (!rst_rd_ni) begin
-1-
169 r_rptr_q <= PtrW'(0);
==>
170 r_rptr_gray_q <= PtrW'(0);
171 end else if (r_rptr_inc) begin
-2-
172 r_rptr_q <= r_rptr_d;
==>
173 r_rptr_gray_q <= r_rptr_gray_d;
174 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
204 if (!rst_rd_ni) begin
-1-
205 r_sram_rptr <= PtrW'(0);
==>
206 end else if (r_sram_rptr_inc) begin
-2-
207 r_sram_rptr <= r_sram_rptr + PtrW'(1);
==>
208 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
279 if (stored) begin
-1-
280 // storage has data. depends on rfifo_ack
281 // rfifo_ack can be replaced to rready_i as `rvalid_o` is 1
282 r_sram_req_o = !r_sramrptr_empty && rfifo_ack;
==>
283 end else begin
284 // storage has no data.
285 // Can send request only when the reader accept the request or no
286 // previous request sent out.
287 r_sram_req_o = !r_sramrptr_empty && !(r_sram_rvalid_i ^ rfifo_ack);
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T44,T42,T32 |
| 0 |
Covered |
T1,T2,T3 |
324 if (!rst_rd_ni) begin
-1-
325 stored <= 1'b 0;
==>
326 rdata_q <= Width'(0);
327 end else if (store_en) begin
-2-
328 stored <= 1'b 1;
==>
329 rdata_q <= rdata_d;
330 end else if (!r_sram_rvalid_i && rfifo_ack) begin
-3-
331 // No request sent, host reads the data
332 stored <= 1'b 0;
==>
333 rdata_q <= Width'(0);
334 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T44,T42,T32 |
| 0 |
0 |
1 |
Covered |
T44,T42,T32 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
349 decval_in = decval[PtrW-1] ? decval_sub : decval;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T86,T39,T87 |
| 0 |
Covered |
T1,T2,T3 |
373 if (grayval[PtrW-1]) begin
-1-
374 gray2dec = dec_tmp_sub;
==>
375 // Override MSB
376 gray2dec[PtrW-1] = 1'b1;
377 unused_decsub_msb = dec_tmp_sub[PtrW-1];
378 end else begin
379 gray2dec = dec_tmp;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T86,T39,T40 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_upload.u_addrfifo
Assertion Details
MinDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
975 |
975 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
NoRAckInEmpty_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
1797 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
NoWAckInFull_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151213017 |
1797 |
0 |
0 |
| T26 |
65289 |
0 |
0 |
0 |
| T28 |
100221 |
0 |
0 |
0 |
| T29 |
103360 |
0 |
0 |
0 |
| T30 |
225457 |
0 |
0 |
0 |
| T31 |
246620 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
25636 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
103582 |
2 |
0 |
0 |
| T45 |
10525 |
0 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
34121 |
0 |
0 |
0 |
| T52 |
56760 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
975 |
975 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
RSramRvalidOneCycle_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
1797 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
RptrGrayOneBitAtATime_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
1797 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
RptrIncDataValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
1797 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
RptrIncrease_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
1797 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
SramRvalid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
457469403 |
1797 |
0 |
0 |
| T21 |
3830 |
0 |
0 |
0 |
| T22 |
4411 |
0 |
0 |
0 |
| T26 |
73673 |
0 |
0 |
0 |
| T27 |
1653 |
0 |
0 |
0 |
| T28 |
771894 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
164598 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
426010 |
2 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
37227 |
0 |
0 |
0 |
| T52 |
230247 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
| T81 |
1347 |
0 |
0 |
0 |
WSramRvalid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151213017 |
151213017 |
0 |
0 |
| T4 |
1688 |
1688 |
0 |
0 |
| T5 |
720 |
720 |
0 |
0 |
| T6 |
12271 |
12271 |
0 |
0 |
| T7 |
12933 |
12933 |
0 |
0 |
| T9 |
39120 |
39120 |
0 |
0 |
| T11 |
22243 |
22243 |
0 |
0 |
| T13 |
22863 |
22863 |
0 |
0 |
| T14 |
14683 |
14683 |
0 |
0 |
| T15 |
216 |
216 |
0 |
0 |
| T16 |
1128 |
1128 |
0 |
0 |
WidthMatch_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
975 |
975 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
WptrGrayOneBitAtATime_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151213017 |
1797 |
0 |
0 |
| T26 |
65289 |
0 |
0 |
0 |
| T28 |
100221 |
0 |
0 |
0 |
| T29 |
103360 |
0 |
0 |
0 |
| T30 |
225457 |
0 |
0 |
0 |
| T31 |
246620 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
25636 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
103582 |
2 |
0 |
0 |
| T45 |
10525 |
0 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
34121 |
0 |
0 |
0 |
| T52 |
56760 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |
WptrIncrease_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151213017 |
1797 |
0 |
0 |
| T26 |
65289 |
0 |
0 |
0 |
| T28 |
100221 |
0 |
0 |
0 |
| T29 |
103360 |
0 |
0 |
0 |
| T30 |
225457 |
0 |
0 |
0 |
| T31 |
246620 |
0 |
0 |
0 |
| T32 |
0 |
9 |
0 |
0 |
| T35 |
0 |
2 |
0 |
0 |
| T38 |
25636 |
0 |
0 |
0 |
| T42 |
0 |
3 |
0 |
0 |
| T44 |
103582 |
2 |
0 |
0 |
| T45 |
10525 |
0 |
0 |
0 |
| T47 |
0 |
4 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T49 |
0 |
6 |
0 |
0 |
| T51 |
34121 |
0 |
0 |
0 |
| T52 |
56760 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T77 |
0 |
3 |
0 |
0 |