Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459754234	2903479	0	0
DataKnown_AKnownEnable	459754234	459618260	0	0
DepthKnown_A	459754234	459618260	0	0
RvalidKnown_A	459754234	459618260	0	0
WreadyKnown_A	459754234	459618260	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	2903479	0	0
T2	3284	100	0	0
T3	1100	0	0	0
T4	1935	0	0	0
T5	7895	0	0	0
T6	15384	1669	0	0
T7	8219	1663	0	0
T8	1120	0	0	0
T9	19600	832	0	0
T10	7938	0	0	0
T11	31698	1860	0	0
T13	0	1665	0	0
T14	0	1663	0	0
T17	0	1663	0	0
T18	0	1670	0	0
T25	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459754234	3215191	0	0
DataKnown_AKnownEnable	459754234	459618260	0	0
DepthKnown_A	459754234	459618260	0	0
RvalidKnown_A	459754234	459618260	0	0
WreadyKnown_A	459754234	459618260	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	3215191	0	0
T2	3284	436	0	0
T3	1100	0	0	0
T4	1935	0	0	0
T5	7895	0	0	0
T6	15384	839	0	0
T7	8219	832	0	0
T8	1120	0	0	0
T9	19600	3629	0	0
T10	7938	0	0	0
T11	31698	3192	0	0
T13	0	834	0	0
T14	0	832	0	0
T17	0	832	0	0
T18	0	839	0	0
T25	0	287	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459754234	187395	0	0
DataKnown_AKnownEnable	459754234	459618260	0	0
DepthKnown_A	459754234	459618260	0	0
RvalidKnown_A	459754234	459618260	0	0
WreadyKnown_A	459754234	459618260	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	187395	0	0
T2	3284	100	0	0
T3	1100	0	0	0
T4	1935	17	0	0
T5	7895	0	0	0
T6	15384	0	0	0
T7	8219	0	0	0
T8	1120	0	0	0
T9	19600	0	0	0
T10	7938	0	0	0
T11	31698	0	0	0
T25	0	100	0	0
T26	0	408	0	0
T30	0	1013	0	0
T31	0	833	0	0
T32	0	500	0	0
T41	0	100	0	0
T42	0	96	0	0
T43	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459754234	403933	0	0
DataKnown_AKnownEnable	459754234	459618260	0	0
DepthKnown_A	459754234	459618260	0	0
RvalidKnown_A	459754234	459618260	0	0
WreadyKnown_A	459754234	459618260	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	403933	0	0
T2	3284	429	0	0
T3	1100	0	0	0
T4	1935	78	0	0
T5	7895	0	0	0
T6	15384	0	0	0
T7	8219	0	0	0
T8	1120	0	0	0
T9	19600	0	0	0
T10	7938	0	0	0
T11	31698	0	0	0
T25	0	306	0	0
T26	0	408	0	0
T30	0	1013	0	0
T31	0	833	0	0
T32	0	1521	0	0
T41	0	305	0	0
T42	0	96	0	0
T43	0	100	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459754234	5643160	0	0
DataKnown_AKnownEnable	459754234	459618260	0	0
DepthKnown_A	459754234	459618260	0	0
RvalidKnown_A	459754234	459618260	0	0
WreadyKnown_A	459754234	459618260	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	5643160	0	0
T1	1187	53	0	0
T2	3284	1	0	0
T3	1100	1	0	0
T4	1935	60	0	0
T5	7895	32	0	0
T6	15384	52	0	0
T7	8219	359	0	0
T8	1120	27	0	0
T9	19600	522	0	0
T10	7938	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459754234	11679606	0	0
DataKnown_AKnownEnable	459754234	459618260	0	0
DepthKnown_A	459754234	459618260	0	0
RvalidKnown_A	459754234	459618260	0	0
WreadyKnown_A	459754234	459618260	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	11679606	0	0
T1	1187	53	0	0
T2	3284	1	0	0
T3	1100	1	0	0
T4	1935	251	0	0
T5	7895	32	0	0
T6	15384	207	0	0
T7	8219	359	0	0
T8	1120	27	0	0
T9	19600	2311	0	0
T10	7938	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459754234	459618260	0	0
T1	1187	1103	0	0
T2	3284	3207	0	0
T3	1100	1031	0	0
T4	1935	1847	0	0
T5	7895	7807	0	0
T6	15384	15288	0	0
T7	8219	8131	0	0
T8	1120	1059	0	0
T9	19600	19524	0	0
T10	7938	5611	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0