Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3592572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4339288

1

T2

1

T3

20

T4

88

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4266667	1			T1	1		T2	77		T3	1
values[0x0]	1830562	1			T3	15		T4	38		T5	46
values[0x1]	1834631	1			T3	10		T4	39		T5	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2544477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5387383

1

T2

23

T3

21

T4

152

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30754	1			T6	7		T12	4		T13	3
valid_sources[0x01]	30398	1			T3	1		T6	2		T12	3
valid_sources[0x02]	30744	1			T12	2		T13	11		T19	9
valid_sources[0x03]	29215	1			T6	3		T12	1		T13	7
valid_sources[0x04]	27334	1			T6	4		T10	2		T12	5
valid_sources[0x05]	32282	1			T12	1		T13	2		T18	42
valid_sources[0x06]	30782	1			T6	3		T12	2		T13	1
valid_sources[0x07]	31573	1			T6	6		T12	1		T13	5
valid_sources[0x08]	31543	1			T5	4		T6	5		T12	3
valid_sources[0x09]	30402	1			T6	1		T12	1		T13	1
valid_sources[0x0a]	31558	1			T12	5		T13	2		T18	15
valid_sources[0x0b]	35056	1			T12	1		T18	27		T19	11
valid_sources[0x0c]	29673	1			T5	2		T6	9		T12	3
valid_sources[0x0d]	29565	1			T6	14		T12	3		T18	15
valid_sources[0x0e]	39374	1			T12	3		T13	4		T19	6
valid_sources[0x0f]	31690	1			T5	9		T6	3		T12	2
valid_sources[0x10]	29368	1			T6	8		T12	7		T18	34
valid_sources[0x11]	33697	1			T3	1		T6	13		T12	1
valid_sources[0x12]	30107	1			T3	1		T6	3		T10	7
valid_sources[0x13]	29378	1			T6	3		T12	3		T19	9
valid_sources[0x14]	33097	1			T6	2		T12	2		T18	11
valid_sources[0x15]	32383	1			T5	11		T6	2		T12	3
valid_sources[0x16]	29825	1			T6	2		T12	2		T13	3
valid_sources[0x17]	26566	1			T6	2		T10	4		T12	2
valid_sources[0x18]	33460	1			T6	6		T12	7		T13	1
valid_sources[0x19]	28855	1			T6	1		T10	3		T12	2
valid_sources[0x1a]	29731	1			T6	1		T12	2		T13	6
valid_sources[0x1b]	31624	1			T6	2		T12	5		T13	3
valid_sources[0x1c]	29271	1			T5	4		T6	8		T10	1
valid_sources[0x1d]	29095	1			T6	2		T12	3		T13	3
valid_sources[0x1e]	29847	1			T6	4		T12	7		T13	2
valid_sources[0x1f]	29744	1			T6	6		T12	4		T13	2
valid_sources[0x20]	37047	1			T12	4		T13	5		T18	1
valid_sources[0x21]	34798	1			T5	6		T6	3		T12	3
valid_sources[0x22]	31368	1			T6	4		T10	7		T12	3
valid_sources[0x23]	28796	1			T5	5		T6	7		T10	1
valid_sources[0x24]	28406	1			T12	2		T13	2		T18	27
valid_sources[0x25]	33318	1			T6	7		T12	10		T13	1
valid_sources[0x26]	27506	1			T6	8		T12	5		T13	1
valid_sources[0x27]	28521	1			T6	17		T12	4		T18	22
valid_sources[0x28]	30563	1			T10	2		T12	4		T18	9
valid_sources[0x29]	38191	1			T6	3		T10	2		T12	4
valid_sources[0x2a]	29554	1			T6	2		T9	1		T12	4
valid_sources[0x2b]	28706	1			T2	77		T6	8		T12	1
valid_sources[0x2c]	30138	1			T3	2		T12	4		T13	12
valid_sources[0x2d]	32147	1			T6	7		T12	5		T13	1
valid_sources[0x2e]	29001	1			T6	4		T9	1		T12	7
valid_sources[0x2f]	35866	1			T6	2		T12	2		T13	10
valid_sources[0x30]	30342	1			T6	10		T10	5		T12	3
valid_sources[0x31]	29060	1			T6	4		T10	1		T12	4
valid_sources[0x32]	30356	1			T6	2		T12	4		T13	5
valid_sources[0x33]	30428	1			T5	1		T6	1		T12	4
valid_sources[0x34]	27832	1			T6	2		T12	3		T13	4
valid_sources[0x35]	37126	1			T6	4		T10	2		T12	2
valid_sources[0x36]	28901	1			T5	4		T6	8		T10	1
valid_sources[0x37]	28549	1			T5	6		T6	3		T12	3
valid_sources[0x38]	32490	1			T6	1		T12	4		T19	17
valid_sources[0x39]	32172	1			T10	5		T12	5		T13	6
valid_sources[0x3a]	27636	1			T10	8		T12	3		T13	3
valid_sources[0x3b]	30820	1			T3	1		T6	4		T10	3
valid_sources[0x3c]	33088	1			T6	5		T12	7		T13	8
valid_sources[0x3d]	34222	1			T6	9		T10	1		T12	1
valid_sources[0x3e]	29345	1			T3	1		T6	6		T12	1
valid_sources[0x3f]	28950	1			T5	1		T6	1		T12	4
valid_sources[0x40]	30184	1			T6	3		T12	2		T13	3
valid_sources[0x41]	29146	1			T5	3		T6	5		T10	1
valid_sources[0x42]	30094	1			T3	1		T12	3		T13	4
valid_sources[0x43]	30223	1			T5	11		T6	4		T12	2
valid_sources[0x44]	28810	1			T6	1		T12	3		T13	5
valid_sources[0x45]	30135	1			T6	3		T12	3		T13	4
valid_sources[0x46]	28614	1			T6	5		T12	2		T13	5
valid_sources[0x47]	31448	1			T6	10		T10	3		T12	4
valid_sources[0x48]	28901	1			T6	12		T12	3		T13	1
valid_sources[0x49]	28714	1			T6	8		T12	5		T13	5
valid_sources[0x4a]	30997	1			T12	9		T19	24		T21	4
valid_sources[0x4b]	32469	1			T6	4		T10	3		T12	2
valid_sources[0x4c]	29503	1			T12	2		T19	5		T21	4
valid_sources[0x4d]	36537	1			T10	14		T12	4		T13	4
valid_sources[0x4e]	27975	1			T6	3		T12	5		T13	2
valid_sources[0x4f]	30777	1			T3	1		T5	2		T6	3
valid_sources[0x50]	31294	1			T6	2		T9	2		T12	5
valid_sources[0x51]	29034	1			T6	3		T9	1		T10	1
valid_sources[0x52]	31869	1			T3	1		T6	7		T10	7
valid_sources[0x53]	31061	1			T6	3		T12	4		T13	3
valid_sources[0x54]	31918	1			T6	12		T12	2		T13	1
valid_sources[0x55]	31689	1			T5	3		T12	6		T19	5
valid_sources[0x56]	26813	1			T6	2		T12	7		T13	4
valid_sources[0x57]	28726	1			T6	4		T10	3		T12	4
valid_sources[0x58]	31944	1			T3	1		T5	2		T6	3
valid_sources[0x59]	29604	1			T6	4		T10	3		T12	2
valid_sources[0x5a]	27767	1			T12	4		T13	1		T19	11
valid_sources[0x5b]	34448	1			T3	1		T6	3		T12	2
valid_sources[0x5c]	29990	1			T6	3		T9	1		T10	5
valid_sources[0x5d]	29245	1			T6	2		T12	3		T13	1
valid_sources[0x5e]	29417	1			T6	5		T12	3		T13	2
valid_sources[0x5f]	28699	1			T5	2		T6	1		T12	1
valid_sources[0x60]	31696	1			T6	1		T10	2		T12	5
valid_sources[0x61]	35472	1			T3	2		T6	4		T12	1
valid_sources[0x62]	31455	1			T6	6		T12	6		T13	7
valid_sources[0x63]	32900	1			T6	7		T12	5		T13	7
valid_sources[0x64]	30678	1			T5	5		T6	1		T10	1
valid_sources[0x65]	30710	1			T12	5		T19	7		T21	3
valid_sources[0x66]	33115	1			T5	2		T12	4		T13	6
valid_sources[0x67]	30510	1			T6	5		T12	3		T13	5
valid_sources[0x68]	29406	1			T5	3		T12	3		T13	8
valid_sources[0x69]	33041	1			T6	6		T9	1		T12	2
valid_sources[0x6a]	30428	1			T6	6		T10	4		T12	4
valid_sources[0x6b]	32619	1			T3	1		T10	6		T12	3
valid_sources[0x6c]	29232	1			T3	1		T6	2		T12	1
valid_sources[0x6d]	28726	1			T12	5		T13	6		T19	1
valid_sources[0x6e]	30273	1			T12	3		T18	2		T19	14
valid_sources[0x6f]	31500	1			T6	10		T12	4		T19	12
valid_sources[0x70]	30332	1			T6	6		T12	3		T13	7
valid_sources[0x71]	30939	1			T6	12		T12	2		T13	4
valid_sources[0x72]	33914	1			T10	2		T12	3		T13	1
valid_sources[0x73]	28033	1			T6	5		T10	3		T12	5
valid_sources[0x74]	31020	1			T3	1		T6	1		T12	4
valid_sources[0x75]	29953	1			T6	1		T12	3		T13	1
valid_sources[0x76]	33751	1			T6	2		T10	1		T12	3
valid_sources[0x77]	32251	1			T6	5		T12	6		T13	1
valid_sources[0x78]	34826	1			T12	2		T13	2		T19	2
valid_sources[0x79]	34540	1			T6	7		T12	3		T13	1
valid_sources[0x7a]	30555	1			T6	6		T12	2		T13	8
valid_sources[0x7b]	29665	1			T6	7		T12	3		T13	8
valid_sources[0x7c]	31278	1			T6	2		T12	5		T13	6
valid_sources[0x7d]	31839	1			T3	1		T6	4		T10	2
valid_sources[0x7e]	32777	1			T3	1		T6	2		T12	2
valid_sources[0x7f]	29372	1			T6	5		T12	2		T18	20
valid_sources[0x80]	29241	1			T6	6		T12	5		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1013195

1

T2

1

T4

58

T5

9

values[0x0]

all_enables

biggest_size

1674167

1

T3

14

T4

17

T5

46

values[0x1]

all_enables

biggest_size

1651926

1

T3

6

T4

13

T5

54