Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3617017

1

T1

1

T2

76

T3

6

full_word

4338677

1

T2

1

T3

20

T4

88

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7955344	1			T1	1		T2	77		T3	26
auto[TlIntgErrCmd]	108	1			T118	1		T119	5		T120	4
auto[TlIntgErrData]	131	1			T118	3		T119	8		T120	3
auto[TlIntgErrBoth]	111	1			T118	6		T119	7		T120	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4270887

1

T1

1

T2

77

T3

1

auto[1]

3684807

1

T3

25

T4

77

T6

878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3257308	1			T1	1		T2	76		T3	1
auto[TlIntgErrNone]	partial	auto[1]	359398	1			T3	5		T4	47		T6	1
auto[TlIntgErrNone]	full_word	auto[0]	1013415	1			T2	1		T4	58		T6	1
auto[TlIntgErrNone]	full_word	auto[1]	3325223	1			T3	20		T4	30		T6	877
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T119	3		T120	2		T213	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T119	1		T120	1		T175	8
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T118	1		T120	1		T214	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T119	1		T175	3		T211	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T118	2		T119	4		T120	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T119	2		T213	1		T175	5
auto[TlIntgErrData]	full_word	auto[0]	9	1			T213	1		T214	2		T215	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T118	1		T119	2		T211	3
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T118	4		T119	3		T213	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T118	2		T119	3		T120	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T216	1		T217	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T119	1		T175	1		T214	1